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D at a S h e e t , V 1. 2 , M ay 2 00 2
TC1775
32-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
Edition 2002-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2002.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D at a S h e e t , V 1. 2 , M ay 2 00 2
TC1775
32-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
TC1775 Data Sheet Preliminary Revision History: Previous Versions: Page - 36 54 59 60 66 68, 69, 70 71 73 73 76 77 78 80 81 82, 83
2002-05 V1.1, 2001-08; V1.0, 2001-08;
V1.2
Subjects (major changes since last revision) Status of data sheet changed from "Advance Information" into "Preliminary" ADC features: example of 10-bit ADC conversion time added Note below Figure 16 added Column "Jitter" in Table 8 removed; the jitter is now defined in "PLL Parameters" on Page 82 and Figure 31; 2nd footnote for Table 8 added Note on bottom extended "... specified by the crystal suppliers:" Section "Package Parameters" added Definition and values for pull-up/pull-down currents changed Curves for pull-up/pull-down characteristics added Formulas for conversion time tC corrected; fANA min./max. specification added Definition of IAOV and kA improved Note 1) for IOZ added
Changes from V1.1, 2001-08 to V1.2, 2002-05
IDD max corrected; IDD active for VDDSB added; note for IID and ISL added tRFAnom (typ.) added
Figure 29 corrected Figure 30 corrected PLL specification and parameters completed
84, 87, 89, Several AC timing parameter values added or corrected: t10, t11, t15, t20, 92, 94, 95 t21, t25, t45, t46, t47, t55, t61, t62 95 several 84 89 90 95 Definition of t61 and t62 changed Formal changes Reference for t31 and t32 to Page 90 added
Changes from V1.0, 2001-08 to V1.1, 2001-08
t50 and t51 changed into TBD; note changed into "Will be guaranteed ..." t31 and t32 (Data setup/hold to CLKIN in burst mode timing) changed;
note 1) added
t61 and t62 changed into TBD; note changed into "Will be guaranteed ..."
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Preliminary
32-Bit Single-Chip Microcontroller TriCore Family
TC1775
* High Performance 32-bit TriCore CPU with 4-Stage Pipeline - 25 ns Instruction Cycle Time at 40 MHz CPU Clock * Dual Issue super-scalar implementation - Instruction triple issue * Circular Buffer and bit-reverse addressing modes for DSP algorithms * Flexible multi-master interrupt system * Very fast interrupt response time * Hardware controlled context switch for task switch and interrupts * 72 Kbytes of on-chip SRAM for data and time critical code * Independent Peripheral Control Processor (PCP) for low level driver support with 20 Kbytes code/parameter memory * Built-in calibration support * On-chip Flexible Peripheral Interface Bus (FPI Bus) for interconnections of functional units * Flexible External Bus Interface Unit (EBU) used for - Communication with external data memories and peripheral units - Instruction fetches from external Burst Flash program memories * On-Chip Peripheral Units - General Purpose Timer Array (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex I/O management - Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/counters - Two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) with baud rate generator, parity, framing and overrun error detection - Two High Speed Synchronous Serial Channels (SSC0, SSC1) with programmable data length and shift direction - TwinCAN module with two interconnected CAN nodes for high efficiency data handling via FIFO buffering and gateway data transfer - Serial Data Link module (SDLM) compliant to SAE Class B J1850 specification - Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit resolution and 16 analog inputs each - Watchdog Timer and System Timer - Real Time Clock * Eleven 16-bit digital I/O ports and two 16-bit analog ports * On-chip Debug Support * Power Management System * Clock Generation Unit with PLL * Ambient temperature under bias: -40 C to +125 C * P-BGA-329 package
Data Sheet 1 V1.2, 2002-05
TC1775
Preliminary Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the package and the type of delivery. The TC1775 is available with the following ordering code: Type Ordering Code Package Description 32-Bit Single-Chip Microcontroller 40 MHz -40 C to +125 C
SAK-TC1775-L40E Q67121-C2285-A701 P-BGA-329
Data Sheet
2
V1.2, 2002-05
Figure 1
Port 5
OCDS
FPI Interface
Port 12
5
Port 0
Port 1
Port 11
Port 10
16 P o rt 7 16 16 P o rt 6
16 16 16 8 2
2
3 P o rt 1 3 16
3
4 P ort 4
12
16 P ort 3 16 EBU C on trol 6 10 A d d re ss [2 5:16 ]
P o rt 9
P o rt 8
16
16
Port 2
Data Sheet
DM U (Data M em ory Unit) 128 32 KB SRAM + 8 K B S tan d -b y S R A M (O v erlay F u nc tio na lity ) T ra ce & OCDS In te rrup t 8 K B B oo t R O M 32 K B S cratch P a d R A M 1 K B In stru ction C a ch e TriC ore CPU 64 PM U (Program M em ory U nit)
Preliminary
Block Diagram
V DD V SS
O CDSE SC U FP I B u s 4 K D a ta-S R A M PLL 32
C on trol
9
B R K IN
BRKO UT
f C P U m ax =
40 M H z 4 XTAL1 XTAL2 C o ntro l
JT A G IO PCP C o re In te rru pt BCU 1 6 K C od e-S R A M STM F P I B us 32 RTC
5
16
(P W R ) P ow e rW a tc hd o gR es et
TC1775 Block Diagram
f R T C = 32 kH z
16
16 C e rb eru s & JT A G
3
A DC 0 G PTU ASC1 ASC0 SSC1 SSC 0 Tw in C AN J1850
XTAL3 XTAL4 C L K IN CLKO UT 16 1 6 A dd r./ D a ta [1 5 :0] 16 EB U (E x te rn al B us U n it) 1 6 A dd r./ D a ta (31 :1 6] 16 16 A dd r. [1 5 :0]
2
16
2
2
5
16
16
G PTA
AD C1
16
16
V1.2, 2002-05
TC1775
M C B 0 4671
TC1775
Preliminary Logic Symbol
TESTMODE CLKIN CLKOUT HDRST PORST General Control NMI CFG BYPASS CLKSEL N.C.1 N.C.2 XTAL1 XTAL2 XTAL3 XTAL4 3 3 7 4 Port 0 16-Bit Port 1 16-Bit Port 2 16-Bit Port 3 16-Bit Port 4 16-Bit Port 5 16-Bit Port 6 16-Bit Port 7 16-Bit Port 8 16-Bit Port 9 16-Bit Port 10 16-Bit Port 11 16-Bit Port 12 16-Bit Port 13 16-Bit
Alternate Functions
External Bus Interface
TRACE
ADC0
ADC1
Oscillators / PLL
VDDOSC VSSOSC VDDPLL VSSPLL
TRST TCK TDI TDO TMS OCDSE BRKIN BRKOUT
TC 1775
GPTA
JTAG / OCDS
ADC0/1 J1850 / ASC0/1 GPTU / SSC0/1 / CAN
VDD VDDP05
Digital Circuitry Power Supply
10 5 6 2 29
VDDP813 VDDSRAM VDDSB VSS VDDSC
VAREF0 VAGND0 VDDA0 VSSA0 VAREF1 VAGND1 VDDA1 VSSA1
ADC0 Analog Power Supply
ADC0 / ADC1 Analog Power Supply
VSSSC VDDM VSSM
ADC1 Analog Power Supply
MCA04679
Figure 2
TC1775 Logic Symbol
Data Sheet
4
V1.2, 2002-05
TC1775
Preliminary Pin Configuration
1
2
3
4 AN 3 AN 4 AN 1 AN 18 AN 22
5 AN 6 AN 7 AN 5 AN 2
6 AN 9 AN 10 AN 8
7 AN 11 AN 13 AN 14 AN 12
8 AN 15
9
10 P12. 13 P12. 12 P12. 11 N .C . 1
11 P 12 . 9 P 12 . 7 P 12 . 8 P 12 . 10
12 P 1 2. 5 P 1 2. 6 P 1 2. 4
13 P 1 2. 1 P 1 2. 2 P 1 2. 3 P 1 2. 0
14 P13 15
15 P 13 . 11 13
16 P 13 . 8 P 13 . 9 P 13 . 10
17 P 1 3. 4 P 1 3. 6 P 1 3. 7 P 1 3. 5
18 P 1 3. 2 P 1 3. 3 P 1 3. 1
19 P11. 15 P13. 0 P11. 14 P11. 11
20 P 11 . 12 P 11 . 13 P 11 . 10 P 11 . 7 P 10 . 15
21 P 1 1. 8 P 1 1. 9 P 1 1. 2 N .C . 2 P 1 0. 12 P 1 0. 9 P 1 0. 3 P 1 0. 0
22 P 1 1. 5 P 1 1. 6 P 1 1. 0 P 1 0. 13 P 1 0. 10 P 1 0. 7 P 1 0. 4 P 1 0. 1
23 P11. 4 P11. 3 P11. 1 P10. 14 P10. 11 P10. 8 P10. 6 P10. 2 A B C D E F G H
A V DDSC V SSSC V SSM B C D E F G AN 16 AN 19 AN 23 AN 26 AN 29 AN 31 AN 17 AN 20 AN 24 AN 27 AN 30 AN 0
V SSA0
V A GN D0 P 1 2 .
15 14
V D D S B P 13 .
N .C . 2 P 13 . 14 P 13 . 12
V DDM
AN 21 AN 25 AN 28
V A RE F0 P 1 2 . V DD
P 81 3
V DD
V DDA0
V DD
P 81 3
V DD
V DD
P 81 3
V SS
V SS
V DD
P 10 . 5
V A REF1 V S S A 1 V A G ND1
P 1 .0 P 1 .4 P 1 .7 P 1 .9 P 1.1 P 1.5 N .C . 2 P 1 .1 0
H V DDA1 J K L P 1.2 P 1.6 P 1.8
V DD
P 05
V DD
P813
P 1 .3
P 9.1 4 P 9 .1 2 P 9 .13 P 9.1 5 J
V DD
N .C . 2
V SS V SS V SS V SS V SS
V SS V SS V SS V SS V SS
V SS V SS V SS V SS V SS
V SS V SS V SS V SS V SS
V SS V SS V SS V SS V SS
V DD
P 9.8
P 9 .9 P 9 .6 P 9 .2 P 9 .1
P 9 .10 P 9.1 1 K P 9 .5 P 9 .4 P 9 .0 P 9 .7 P 9 .3 L M
M P 1.12 P 1.1 3 P 1 .1 1 N P R T P 0.0 P 0.4 C LK OUT C LK IN P 1.1 4 P 1 .1 5 P 0 .3 P 0 .6 P 0 .9 P 0.2 P 0.5 P 0.8
V DD
P 05
V DD
P813
P 0 .1
P 8.1 4
P 8.1 5 N
V DD
P 0 .7
V DD
P 8.8
P 8 .1 3 P 8 .12 P 8.1 1 P P 8 .1 0 P 8 .6 P 8 .3 P 8 .9 P 8 .5 P 8 .2 P 8 .7 P 8 .4 P 8 .0 CLK S E L1 C FG 3 C FG 0 R T U V W Y AA
V DD
P 05
V DD
P813
U P 0.13 P 0.1 1 P 0 .1 0 P 0 .1 2 V P 0.15 P 0.1 4 W Y AA P 4.2 P 4.5 P 4.9 P 4 .1 P 4 .4 P 4 .8 P 4.0 P 4.3 P 4.7 P 4 .1 0 P 2.0 N .C . 2 3
P 8.1
V DD
P 4 .6 P 4 .1 5 P 2 .1 P 2 .4 P 2 .3 4 P 2 .2 P 2 .5 P 2 .7 P 2 .6 5
V SS
HD RST
CLK C LK S E L0 S E L 2 C FG 2 PO RST BY PASS CFG 1
V SS
P 2 .8
P 2 .1 2 P 2 .1 4
V DD
P05
P 3 .3 P 3 .5 P 3 .4 P 3 .2 9
V DD
P 3 .8 P 3 .7 P 3 .6 10
P 3.9
V DD
P05
P 5 .3 P 5 .1 P 5 .0 P 5 .2 13
N .C . 1 P 5 .4 P 5 .5 P 5 .6 14
P 5.8 P 5.7 N .C . 1 P 5.9 15
N .C . 2
P 5 .1 5
V DD
TD O
OCD SE
NMI
P 3 .1 P 3 .0
P 3 .1 2 P 3 .1 3 P 3 .1 1 P 3 .1 5 P 3 .1 0 P 3 .1 4 11 12
P 5.1 0 P 5 .1 3 P 5.1 1 P 5 .1 4 P 5.1 2 16
TR ST X TAL 4 TC K TDI 19 TMS BRK IN 20
V SS
OSC
VDD
P LL
V SS
PLL
A B P 4.11 P 4.1 4 A C P 4.12 P 4.1 3 1 2
P 2.1 0 P 2 .1 3 P 2 .9 6
V DD
SR AM
XTA L 3
N .C . T E S T AB 2 MODE XTAL XTAL 2 1 22 23 AC
P 2 .1 1 P 2 .1 5 7 8
V DD
SRAM
BRK OUT 18
V DD
OSC
17
21
M C P 04680
Figure 3
TC1775 Pinning: P-BGA-329 Package (top view)
Data Sheet
5
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P0 Pin Definitions and Functions Pin In Functions Out I/O Port 0 Port 0 serves as 16-bit general purpose I/O port or as lower external address/data bus AD[15:0] (multiplexed bus mode) or data bus D[15:0] (demultiplexed bus mode) for the EBU. Port 0 is used as data input by an external bus master when accessing modules on the internal FPI Bus. AD0 / D0 Address/data bus line 0 / Data bus line 0 AD1 / D1 Address/data bus line 1 / Data bus line 1 AD2 / D2 Address/data bus line 2 / Data bus line 2 AD3 / D3 Address/data bus line 3 / Data bus line 3 AD4 / D4 Address/data bus line 4 / Data bus line 4 AD5 / D5 Address/data bus line 5 / Data bus line 5 AD6 / D6 Address/data bus line 6 / Data bus line 6 AD7 / D7 Address/data bus line 7 / Data bus line 7 AD8 / D8 Address/data bus line 8 / Data bus line 8 AD9 / D9 Address/data bus line 9 / Data bus line 9 AD10 / D10 Address/data bus line 10 / Data bus line 10 AD11 / D11 Address/data bus line 11 / Data bus line 11 AD12 / D12 Address/data bus line 12 / Data bus line 12 AD13 / D13 Address/data bus line 13 / Data bus line 13 AD14 / D14 Address/data bus line 14 / Data bus line 14 AD15 / D15 Address/data bus line 15 / Data bus line 15
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15
N1 N4 P3 P2 P1 R3 R2 R4 T3 T2 U3 U2 U4 U1 V2 V1
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Data Sheet
6
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P1 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 1 Port 1 serves as 16-bit general purpose I/O port or as upper external address/data bus AD[31:16] (multiplexed bus mode) or data bus D[31:16] (demultiplexed bus mode) for the EBU. Port 1 is used as data input by an external bus master when accessing modules on the internal FPI Bus. AD16 / D16 Address/data bus line 16 / Data bus line 16 AD17 / D17 Address/data bus line 17/ Data bus line 17 AD18 / D18 Address/data bus line 18 / Data bus line 18 AD19 / D19 Address/data bus line 19 / Data bus line 19 AD20 / D20 Address/data bus line 20 / Data bus line 20 AD21 / D21 Address/data bus line 21 / Data bus line 21 AD22 / D22 Address/data bus line 22 / Data bus line 22 AD23 / D23 Address/data bus line 23 / Data bus line 23 AD24 / D24 Address/data bus line 24 / Data bus line 24 AD25 / D25 Address/data bus line 25 / Data bus line 25 AD26 / D26 Address/data bus line 26 / Data bus line 26 AD27 / D27 Address/data bus line 27 / Data bus line 27 AD28 / D28 Address/data bus line 28 / Data bus line 28 AD29 / D29 Address/data bus line 29 / Data bus line 29 AD30 / D30 Address/data bus line 30 / Data bus line 30 AD31 / D31 Address/data bus line 31 / Data bus line 31
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15
H2 H3 J1 J4 J2 J3 K1 K2 L1 L2 L3 M3 M1 M2 N2 N3
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Data Sheet
7
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P2 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 2 Port 2 serves as 16-bit general purpose I/O port or as lower external address bus for the EBU. When used as address bus, it outputs the addresses A[15:0] of an external access in demultiplexed bus mode. Port 2 is used as address input by an external bus master when accessing modules on the internal FPI Bus. A0 Address bus line 0 A1 Address bus line 1 A2 Address bus line 2 A3 Address bus line 3 A4 Address bus line 4 A5 Address bus line 5 A6 Address bus line 6 A7 Address bus line 7 A8 Address bus line 8 A9 Address bus line 9 A10 Address bus line 10 A11 Address bus line 11 A12 Address bus line 12 A13 Address bus line 13 A14 Address bus line 14 A15 Address bus line 15
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15
AB3 AA4 Y5 AC4 AB4 AA5 AC5 AB5 AA6 AC6 AB6 AC7 Y7 AB7 AA7 AC8
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Data Sheet
8
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P3 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 3 Port 3 serves as 16-bit general purpose I/O port or as upper external address bus for the EBU. When used as address bus, it outputs the addresses A[25:16] of an external access in demultiplexed bus mode. P3[9:0] is used as address input by an external bus master when accessing modules on the internal FPI Bus. Port 3 also provides chip select output lines CS0 - CS3, CSEMU, and CSOVL. A16 Address bus line 16 A17 Address bus line 17 A18 Address bus line 18 A19 Address bus line 19 A20 Address bus line 20 A21 Address bus line 21 A22 Address bus line 22 A23 Address bus line 23 A24 Address bus line 24 A25 Address bus line 25 CS3 Chip select output line 3 Chip select output line 2 CS2 CS1 Chip select output line 1 Chip select output line 0 CS0 CSEMU Chip select output for emulator region CSOVL Chip select output for emulator overlay memory
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.101) P3.111) P3.121) P3.131) P3.141) P3.151)
AB8 AA8 AC9 Y9 AB9 AA9 AC10 AB10 AA10 Y11 AC11 AB11 AA11 AA12 AC12 AB12
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O
Data Sheet
9
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P4 P4.01) P4.11) P4.22) P4.31) P4.41) P4.51) P4.61) P4.71) P4.81) P4.91) P4.101) P4.111) P4.121) P4.131) P4.141) P4.151) Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 4 Port 4 is used as general purpose I/O port but also serves as control bus for the EBU control lines. RD Read control line RD/WR Write control line ALE Address latch enable output ADV Address valid output Byte control line 0 BC0 Byte control line 1 BC1 BC2 Byte control line 2 Byte control line 3 BC3 Wait input / End of burst input WAIT/IND BAA Burst address advance output Chip select FPI input CSFPI Hold request input HOLD HLDA Hold acknowledge input/output Bus request output BREQ Code fetch status output CODE SVM Supervisor mode input/output The CODE signal has the same timing as the CSx signals which are located at Port 3.
V3 W2 W1 W3 Y2 Y1 W4 Y3 AA2 AA1 AA3 AB1 AC1 AC2 AB2 Y4
I/O I/O O O I/O I/O I/O I/O I O I I I/O O O I/O
Data Sheet
10
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P5 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 5 Port 5 serves as 16-bit general purpose I/O port or as CPU or PCP trace output port for the OCDS logic. TRACE0 CPU or PCP trace output 0 TRACE1 CPU or PCP trace output 1 TRACE2 CPU or PCP trace output 2 TRACE3 CPU or PCP trace output 3 TRACE4 CPU or PCP trace output 4 TRACE5 CPU or PCP trace output 5 TRACE6 CPU or PCP trace output 6 TRACE7 CPU or PCP trace output 7 TRACE8 CPU or PCP trace output 8 TRACE9 CPU or PCP trace output 9 TRACE10 CPU or PCP trace output 10 TRACE11 CPU or PCP trace output 11 TRACE12 CPU or PCP trace output 12 TRACE13 CPU or PCP trace output 13 TRACE14 CPU or PCP trace output 14 TRACE15 CPU or PCP trace output 15
P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15
AB13 AA13 AC13 Y13 AA14 AB14 AC14 AA15 Y15 AC15 AA16 AB16 AC16 AA17 AB17 Y17
O O O O O O O O O O O O O O O O
Data Sheet
11
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P6 Pin Definitions and Functions (cont'd) Pin In Functions Out I Port 6 Port 6 provides the analog input lines for the AD Converter 0 (ADC0). AN0 Analog input 0 / VAREF[1] input for ADC0 AN1 Analog input 1 / VAREF[2] input for ADC0 AN2 Analog input 2 / VAREF[3] input for ADC0 AN3 Analog input 3 AN4 Analog input 4 AN5 Analog input 5 AN6 Analog input 6 AN7 Analog input 7 AN8 Analog input 8 AN9 Analog input 9 AN10 Analog input 10 AN11 Analog input 11 AN12 Analog input 12 AN13 Analog input 13 AN14 Analog input 14 AN15 Analog input 15 Port 7 Port 7 provides the analog input lines for the AD Converter 1 (ADC1). AN16 Analog input 16 / VAREF[1] input for ADC1 AN17 Analog input 17 / VAREF[2] input for ADC1 AN18 Analog input 18 / VAREF[3] input for ADC1 AN19 Analog input 19 AN20 Analog input 20 AN21 Analog input 21 AN22 Analog input 22 AN23 Analog input 23 AN24 Analog input 24 AN25 Analog input 25 AN26 Analog input 26 AN27 Analog input 27 AN28 Analog input 28 AN29 Analog input 29 AN30 Analog input 30 AN31 Analog input 31
P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P6.8 P6.9 P6.10 P6.11 P6.12 P6.13 P6.14 P6.15 P7
B3 C4 D5 A4 B4 C5 A5 B5 C6 A6 B6 A7 D7 B7 C7 A8
I I I I I I I I I I I I I I I I I
P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P7.8 P7.9 P7.10 P7.11 P7.12 P7.13 P7.14 P7.15
B1 B2 D4 C1 C2 D3 E4 D1 D2 E3 E1 E2 F3 F1 F2 G1
I I I I I I I I I I I I I I I I
Data Sheet
12
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P8 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 8 Port 8 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN0 / OUT0 line of GPTA IN1 / OUT1 line of GPTA IN2 / OUT2 line of GPTA IN3 / OUT3 line of GPTA IN4 / OUT4 line of GPTA IN5 / OUT5 line of GPTA IN6 / OUT6 line of GPTA IN7 / OUT7 line of GPTA IN8 / OUT8 line of GPTA IN9 / OUT9 line of GPTA IN10 / OUT10 line of GPTA IN11 / OUT11 line of GPTA IN12 / OUT12 line of GPTA IN13 / OUT13 line of GPTA IN14 / OUT14 line of GPTA IN15 / OUT15 line of GPTA Port 9 Port 9 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN16 / OUT16 line of GPTA IN17 / OUT17 line of GPTA IN18 / OUT18 line of GPTA IN19 / OUT19 line of GPTA IN20 / OUT20 line of GPTA IN21 / OUT21 line of GPTA IN22 / OUT22 line of GPTA IN23 / OUT23 line of GPTA IN24 / OUT24 line of GPTA IN25 / OUT25 line of GPTA IN26 / OUT26 line of GPTA IN27 / OUT27 line of GPTA IN28 / OUT28 line of GPTA IN29 / OUT29 line of GPTA IN30 / OUT30 line of GPTA IN31 / OUT31 line of GPTA
P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 P8.8 P8.9 P8.10 P8.11 P8.12 P8.13 P8.14 P8.15 P9
U23 U20 U22 U21 T23 T22 T21 R23 R20 R22 R21 P23 P22 P21 N20 N23
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 P9.6 P9.7 P9.8 P9.9 P9.10 P9.11 P9.12 P9.13 P9.14 P9.15
N22 N21 M21 M23 M22 L22 L21 L23 L20 K21 K22 K23 J21 J22 J20 J23
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Data Sheet
13
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P10 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 10 Port 10 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN32 / OUT32 line of GPTA IN33 / OUT33 line of GPTA IN34 / OUT34 line of GPTA IN35 / OUT35 line of GPTA IN36 / OUT36 line of GPTA IN37 / OUT37 line of GPTA IN38 / OUT38 line of GPTA IN39 / OUT39 line of GPTA IN40 / OUT40 line of GPTA IN41 / OUT41 line of GPTA IN42 / OUT42 line of GPTA IN43 / OUT43 line of GPTA IN44 / OUT44 line of GPTA IN45 / OUT45 line of GPTA IN46 / OUT46 line of GPTA IN47 / OUT47 line of GPTA Port 11 Port 11 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN48 / OUT48 line of GPTA IN49 / OUT49 line of GPTA IN50 / OUT50 line of GPTA IN51 / OUT51 line of GPTA IN52 / OUT52 line of GPTA IN53 / OUT53 line of GPTA IN54 / OUT54 line of GPTA IN55 / OUT55 line of GPTA IN56 / OUT56 line of GPTA IN57 / OUT57 line of GPTA IN58 / OUT58 line of GPTA IN59 / OUT59 line of GPTA IN60 / OUT60 line of GPTA IN61 / OUT61 line of GPTA IN62 / OUT62 line of GPTA IN63 / OUT63 line of GPTA
P10.0 P10.1 P10.2 P10.3 P10.4 P10.5 P10.6 P10.7 P10.8 P10.9 P10.10 P10.11 P10.12 P10.13 P10.14 P10.15 P11
H21 H22 H23 G21 G22 G20 G23 F22 F23 F21 E22 E23 E21 D22 D23 E20
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
P11.0 P11.1 P11.2 P11.3 P11.4 P11.5 P11.6 P11.7 P11.8 P11.9 P11.10 P11.11 P11.12 P11.13 P11.14 P11.15
C22 C23 C21 B23 A23 A22 B22 D20 A21 B21 C20 D19 A20 B20 C19 A19
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Data Sheet
14
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P12 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 12 Port 12 is a 16-bit bidirectional general purpose I/O port or serves as ADC control port and SDLM/ASC I/O port. AD0EMUX0 ADC0 external multiplexer control 0 AD0EMUX1 ADC0 external multiplexer control 1 AD0EMUX2 ADC0 external multiplexer control 2 AD1EMUX0 ADC1 external multiplexer control 0 AD1EMUX1 ADC1 external multiplexer control 1 AD1EMUX2 ADC1 external multiplexer control 2 AD1EXTIN0 ADC1 external trigger input 0 AD1EXTIN1 ADC1 external trigger input 1 AD0EXTIN0 ADC0 external trigger input 0 AD0EXTIN1 ADC0 external trigger input 1 RXJ1850 SDLM receiver input TXJ1850 SDLM transmitter output RXD0A ASC0 receiver input/output A TXD0A ASC0 transmitter output A RXD1A ASC1 receiver input/output A TXD1A ASC1 transmitter output A
P12.0 P12.1 P12.2 P12.3 P12.4 P12.5 P12.6 P12.7 P12.8 P12.9 P12.10 P12.11 P12.12 P12.13 P12.14 P12.15
D13 A13 B13 C13 C12 A12 B12 B11 C11 A11 D11 C10 B10 A10 C9 B9
O O O O O O I I I I I O I/O O I/O O
Data Sheet
15
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol P13 Pin Definitions and Functions (cont'd) Pin In Functions Out I/O Port 13 Port 13 is a 16-bit bidirectional general purpose I/O port that is also used as input/output for the serial interfaces (ASC, SSC, CAN) and timers (GPTU). GPT0 GPTU I/O line 0 GPT1 GPTU I/O line 1 GPT2 GPTU I/O line 2 RXD0B ASC0 receiver input/output B GPT3 GPTU I/O line 3 TXD0B ASC0 transmitter output B GPT4 GPTU I/O line 4 RXD1B ASC1 receiver input/output B GPT5 GPTU I/O line 5 TXD1B ASC1 transmitter output B GPT6 GPTU I/O line 6 SCLK0 SSC0 clock input/output GPT7 GPTU I/O line 7 MRST0 SSC0 master receive / slave transmit input/output MTSR0 SSC0 master transmit / slave receive output/input SCLK1 SSC1 clock input/output MRST1 SSC1 master receive / slave transmit input/output MTSR1 SSC1 master transmit / slave receive output/input RXDCAN0 CAN receiver input 0 TXDCAN0 CAN transmitter output 0 RXDCAN1 CAN receiver input 1 TXDCAN1 CAN transmitter output 1 PLL Clock Selection Inputs These pins are sampled during power-on reset (PORST = low); they determine the division rate in the feedback path of the PLL (N-Factor). The latched values of these input pins are available in the PLL Clock Control Register PLL_CLC. The combination BYPASS = 1 and CLKSEL[2:0] = 000B during power-on reset is reserved.
P13.0 P13.1 P13.2 P13.3 P13.4 P13.5 P13.6 P13.7
B19 C18 A18 B18 A17 D17 B17 C17
I/O I/O I/O I/O I/O O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I O I O I I I
P13.8 P13.9 P13.10 P13.11 P13.12 P13.13 P13.14 P13.15
A16 B16 C16 A15 D15 B15 C15 A14
CLKSEL0 V21 CLKSEL1 V23 CLKSEL2 V22
Data Sheet
16
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol BYPASS Pin Definitions and Functions (cont'd) Pin W22 In Functions Out I PLL Bypass Control Input BYPASS is used for direct drive mode operation of the clock circuitry. This pin is sampled during power-on reset (PORST = low). Its level is latched into the PLL Clock Control Register PLL_CLC. The combination BYPASS = 1 and CLKSEL[2:0] = 000B during power-on reset is reserved. Operation Configuration Inputs The configuration inputs define the boot options of the TC1775 after a hardware reset operation. JTAG Module Reset/Enable Input A low level at this pin resets and disables the JTAG module. A high level enables the JTAG module. JTAG Module Clock Input JTAG Module Serial Data Input JTAG Module Serial Data Output JTAG Module State Machine Control Input OCDS Enable Input A low level on this pin during power-on reset (PORST = low) enables the on-chip debug support (OCDS). In addition, the level of this pin during power-on reset determines the boot configuration. OCDS Break Input A low level on this pin causes a break in the chip's execution when the OCDS is enabled. In addition, the level of this pin during power-on reset determines the boot configuration. OCDS Break Output A low level on this pin indicates that a programmable OCDS event has occurred. Non-Maskable Interrupt Input A high-to-low transition on this pin causes a NMI-Trap request to the CPU.
CFG0 CFG1 CFG2 CFG3 TRST3)
Y23 Y22 W21 W23 AA19
I I I I I
TCK3) TDI4) TDO TMS4)
AB19 AC19 AA18 AB20
I I O I I
OCDSE4) Y19
BRKIN4)
AC20
I
BRKOUT AC18
O
NMI4)
Y20
I
Data Sheet
17
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol HDRST4) Pin Definitions and Functions (cont'd) Pin W20 In Functions Out I/O Hardware Reset Input/Reset Indication Output Assertion of this bidirectional open-drain pin causes a synchronous reset of the chip through external circuitry. This pin must be driven for a minimum duration. The internal reset circuitry drives this pin in response to a power-on, hardware, watchdog and power-down wake-up reset for a specific period of time. For a software reset, activation of this pin is programmable. Power-on Reset Input A low level on PORST causes an asynchronous reset of the entire chip. PORST is a fully asynchronous level sensitive signal. EBU Clock Input CLKIN must be connected externally with CLKOUT. For finetuning of the external bus interface timing, this external connection can be an external delay circuit. Clock Output Test Mode Select Input For normal operation of the TC1775, this pin should be connected to VDDP05. Oscillator/PLL/Clock Generator Input/Output Pins XTAL1 is the input to the main oscillator amplifier and input to the internal clock generator. XTAL2 is the output of the main oscillator amplifier circuit. For clocking the device from an external source, XTAL1 is driven with the clock signal while XTAL2 is left unconnected. For crystal oscillator operation XTAL1 and XTAL2 are connected to the crystal with the appropriate recommended oscillator circuitry. Real Time Clock Oscillator Input/Output XTAL3 and XTAL4 are the input and the output of the 32 kHz oscillator that is used for the Real Time Clock.
PORST5)
Y21
I
CLKIN
T1
I
CLKOUT TEST MODE4) XTAL1 XTAL2
R1 AB23
O I
AC23 AC22
I O
XTAL3 XTAL4
AB21 AA20
I O
Data Sheet
18
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol Pin Definitions and Functions (cont'd) Pin AC21 AA21 AA22 AA23 In Functions Out - - - - Main Oscillator Power Supply (2.5 V)6)7) Main Oscillator Ground PLL Power Supply (2.5 V)6)7) PLL Ground Ground
VDDOSC VSSOSC VDDPLL VSSPLL VSS
F4, Y6, - V20, D18, K10 to K14, L10 to L14, M10 to M14, N10 to N14, P10 to P14 K4, P4 - V4, D6 Y10 D14 Y18 F20 K20 P20
VDD
Core Power Supply (2.5 V)6)7)
Data Sheet
19
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol Pin Definitions and Functions (cont'd) Pin H4 M4 T4 Y8 Y12 D8 D12 D16 H20 M20 T20 AB18 In Functions Out - Ports 0 to 5 Power Supply (2.5 V)6)7)
VDDP05
VDDP813
-
Port 8-13 and Dedicated Pins Power Supply (3.3 to 5 V)8)
VDDSRAM AC17, - VDDSB VDDSC VSSSC VDDM VSSM VDDA0 VSSA0 VDDA1 VSSA1 VAREF0 VAGND0 VAREF1 VAGND1
B14 A1 A2 C3 A3 D9 A9 H1 G3 C8 B8 G2 G4 - - - - - - - - - - - - -
SRAM (RAMs of DMU, PMU, and PCP) Power Supply (2.5 V)7) Stand-by Power Supply of 8 Kbyte SBSRAM (2.5 V)7) ADC Short Circuit/Broken Wire Logic Power Supply (5 V)8) ADC Short Circuit/Broken Wire Logic Ground ADC Analog Part Power Supply (5 V)8) ADC Analog Part Ground ADC0 Analog Part Power Supply (2.5 V)6)7) ADC0 Analog Part Ground for VDDA0 ADC1 Analog Part Power Supply (2.5 V)6)7) ADC1 Analog Part Ground for VDDA1 ADC0 Reference Voltage8) ADC0 Reference Ground ADC1 Reference Voltage8) ADC1 Reference Ground
Data Sheet
20
V1.2, 2002-05
TC1775
Preliminary Table 1 Symbol N.C.1 Pin Definitions and Functions (cont'd) Pin AB15, D10, Y14 AB22, C14, K3, AC3, L4, D21, Y16 In Functions Out - Not Connected 1 These pins must not be connected. Not Connected 2 For compatibility reasons, these pins should not be connected. Any connection to 5 V does not harm the device.
N.C.2
-
1) 2) 3) 4) 5) 6)
After reset, an internal pull-up device is enabled for this pin. After reset, an internal pull-down device is enabled for this pin. These pins have an internal pull-down device connected. These pins have an internal pull-up device connected. The TC1775 BA11 step has an internal pull-up device connected to this pin. The voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on power supply pins marked with 6) (details see power supply section on Page 62). In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be kept at the same voltage level during normal operating mode. This condition is best achieved by generating the 2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if a separate stand-by power supply VDDSB is used. The voltage on power supply pins marked with 8) has to be raised earlier or at least at the same time as on power supply pins marked with 6) (details see power supply section on Page 62).
7)
8)
Data Sheet
21
V1.2, 2002-05
TC1775
Preliminary Parallel Ports The TC1775 has 196 digital input/output port lines, which are organized into twelve parallel 16-bit ports, Port 0 to Port 5 with 2.5 V nominal voltage (pin class B), and Port 8 to Port 13 with 3.0 to 5.25 V voltage (pin class A). Additionally, 32 analog input port lines are available, which are organized into two parallel 16-bit ports, Port 6 and Port 7. The digital parallel ports can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. Port 0 to Port 5 are especially dedicated for the on-chip External Bus Interface Unit to communicate with external memories, external peripherals, or external debugging devices via an external bus interface. Port 8 to Port 13 can be assigned to the on-chip peripheral units for their specific I/O operations. An overview on the port-to-peripheral unit assignment is shown in Figure 4. Note: For further details on the three pin classes of the TC1775 I/O pins see also Table 10 on Page 64:
A lte rna te F un ction s G P IO A d dre ss /D a ta B u s P o rt 0 A d dre ss /D a ta B u s P o rt 1 A dd res s B u s P o rt 2 A dd res s B u s P o rt 3 B u s C on trol L ine s B u s C on trol L ine s P o rt 4 O C D S T ra ce L ine s P o rt 5 TC 1775 P a ralle l P o rts
G P IO P o rt 8 P o rt 9
A ltern ate F u nc tio ns G PTA G PTA
P o rt 1 0 G P T A P o rt 1 1 G P T A P o rt 1 2 A D C 0 /1 / A S C 0 /1 / S D L M P o rt 1 3 S S C 0 /1 / A S C 0/1 / G PTU / CAN
P ort 6 ADC0
P ort 7 ADC1
M C A 04734
Figure 4
Parallel Ports of the TC1775
Data Sheet
22
V1.2, 2002-05
TC1775
Preliminary Serial Interfaces The TC1775 includes six serial peripheral interface units: - - - - Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1) Two High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) One TwinCAN Interface One J1850 Serial Data Link Interface (SDLM)
Asynchronous/Synchronous Serial Interfaces Figure 5 shows a global view of the functional blocks of the two Asynchronous/ Synchronous Serial interfaces ASC0 and ASC1.
C lo ck C o ntro l
fASC 0
P 12 .12 / RXD0A RXD0 ASC0 M o d ule (K e rne l) TX D 0 P 12 .13 / TXD0A P 13 .2 / RXD0B P 13 .3 / TXD0B P o rt 12 & P o rt 13 C on trol P 12 .14 / RXD1A RXD1 ASC1 M o d ule (K e rne l) P 12 .15 / TXD1A P 13 .4 / RXD1B P 13 .5 / TXD1B
M C B 04485
A d d res s D e co d er
In terru pt C o ntro l
C lo ck C o ntro l
fASC 1
A d d res s D e co d er
TX D 1
In terru pt C o ntro l
Figure 5
General Block Diagram of the ASC Interfaces
Data Sheet
23
V1.2, 2002-05
TC1775
Preliminary Each ASC module, ASC0 and ASC1, communicates with the external world via two pairs of two I/O lines each. The RXD line is the receive data input signal (in Synchronous Mode also output). TXD is the transmit output signal. Clock control, address decoding, and interrupt service request control are managed outside the ASC module kernel. The Asynchronous/Synchronous Serial Interfaces provide serial communication between the TC1775 and other microcontrollers, microprocessors or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock which is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal that can be very accurately adjusted by a prescaler implemented as a fractional divider. Features: * Full duplex asynchronous operating modes - 8-bit or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baud rate from 2.5 Mbit/s to 0.6 Bit/s (@ 40 MHz clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability * Half-duplex 8-bit synchronous operating mode - Baud rate from 5 Mbit/s to 406.9 Bit/s (@ 40 MHz clock) * Double buffered transmitter/receiver * Interrupt generation - On a transmitter buffer empty condition - On a transmit last bit of a frame condition - On a receiver buffer full condition - On an error condition (frame, parity, overrun error) * Two pin pairs RXD/TXD for each ASC available at Port 12 or Port 13
Data Sheet
24
V1.2, 2002-05
TC1775
Preliminary High-Speed Synchronous Serial Interfaces Figure 6 shows a global view of the functional blocks of the two High-Speed Synchronous Serial interfaces SSC0 and SSC1.
Slave Master
C lo ck C o ntro l
fSSC 0
RXD TX D RXD TX D S lav e M as te r P 13 .8 / M TS R 0 P 13 .7 / M R S T0 P 13 .6 / SCLK0
A d d res s D e co de r
SSC0 M o du le (K e rne l)
In terru pt C o ntro l
SCLK
P o rt C on trol Slave Master C lo ck C o ntro l
fSSC 1
RXD TX D RXD TX D S lav e M as te r P 13 .11 / M TS R 1 P 13 .10 / M R S T1 P 13 .9 / SCLK1
A d d res s D e co de r
SSC1 M o du le (K e rne l)
In terru pt C o ntro l
SCLK
M C B 04486
Figure 6
General Block Diagram of the SSC Interfaces
Each of the SSC modules has three I/O lines, located at Port 13. Each of the SSC modules is further supplied by separate clock control, interrupt control, address decoding, and port control logic. The SSC supports full-duplex and half-duplex serial synchronous communication up to 20 Mbit/s (@ 40 MHz module clock). The serial clock signal can be generated by the SSC itself (master mode) or can be received from an external master (slave mode). Data width, shift direction, clock polarity, and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal.
Data Sheet
25
V1.2, 2002-05
TC1775
Preliminary Features: * Master and slave mode operation - Full-duplex or half-duplex operation * Flexible data format - Programmable number of data bits: 2 to 16 bit - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock * Baud rate generation from 20 Mbit/s to 305.18 Bit/s (@ 40 MHz module clock) * Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) * Three-pin interface - Flexible SSC pin configuration
Data Sheet
26
V1.2, 2002-05
TC1775
Preliminary TwinCAN Interface Figure 7 shows a global view of the functional blocks of the TwinCAN module.
C lo ck C o ntro l
fCAN
Tw inC A N M od u le K e rne l B its tre a m P roc es so r
TXDC0 RXDC0 P o rt C o n tro l TXDC1 E rro r H a nd lin g C o ntrol
A d d res s D e co de r SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7
M es sa ge B u ffe rs
P 13 .13 / TXDCAN0 P 13 .12 / RXDCAN0
In terru pt C o ntro l
In terru pt C o ntro l
Tim in g C o n tro l
RXDC1
P 13 .15 / TXDCAN1 P 13 .14 / RXDCAN1
M C B 04674
Figure 7
General Block Diagram of the TwinCAN Module
The TwinCAN module has four I/O lines located at Port 13. The TwinCAN module is further supplied by a clock control, interrupt control, address decoding, and port control logic. The TwinCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames are handled in accordance to CAN specification V2.0 part B (active). Each of the two Full-CAN interfaces can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share the TwinCAN module's resources to optimize the CAN bus traffic handling and to minimize the CPU load. The flexible combination of Full-CAN functionality and the FIFO architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. Improved CAN bus monitoring functionality as well as the increased number of message objects permit precise and convenient CAN bus traffic handling. Depending on the application, each of the thirty-two message objects can be individually assigned to one of the two CAN nodes. Gateway functionality allows automatic data exchange between two separate CAN bus systems to reduce CPU load and improve the real time behavior of the entire system.
Data Sheet
27
V1.2, 2002-05
TC1775
Preliminary The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 Mbit/s. A pair of receive and transmit pins connect each CAN node to a bus transceiver. Features: * * * * Full CAN functionality conforms to CAN specification V2.0 B active Dedicated control registers are provided for each CAN node A data transfer rate up to 1 Mbit/s is supported Flexible and powerful message transfer control and error handling capabilities are implemented * Full-CAN functionality: 32 message objects can be individually - Assigned to one of the two CAN nodes - Configured as transmit or receive objects - Participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm - Setup to handle frames with 11-bit or 29-bit identifiers - Provided with programmable acceptance mask register for filtering - Monitored via a frame counter - Configured to Remote Monitoring Mode * Up to eight individually programmable interrupt nodes can be used * CAN Analyzer Mode for bus monitoring is implemented
Data Sheet
28
V1.2, 2002-05
TC1775
Preliminary Serial Data Link Interface Figure 8 shows a global view of the functional blocks of the Serial Data Link Interface (SDLM).
C lo ck C o ntro l
fSD LM
RXD A d d res s D e co de r S D LM M o du le (K e rne l) TXD P o rt C o n tro l
P 12 .1 0 / R X J1 8 50 P 12 .1 1 / T X J 18 50
In terru pt C o ntro l
M C B 04570
Figure 8
General Block Diagram of the SDLM Interface
The SDLM module communicates with the external world via two I/O lines located at Port 12, the J1850 bus. The RXD line is the receive data input signal and TXD is the transmit data output signal. The Serial Data Link module (SDLM) provides serial communication to a J1850 based serial bus. J1850 bus transceivers must be implemented externally in a system. The SDLM module conforms to the SAE Class B J1850 Specification and is compatible to Class 2 protocol. General SDLM Features: * * * * * * * * Compliant to SAE Class B J1850 Specification Full support of GM Class 2 protocol Variable Pulse Width (VPW) format with 10.4 kbit/s High speed receive/transmit 4x mode with 41.6 kbit/s Digital noise filter Support of single byte headers or consolidated headers CRC generation and check Support of Block Mode for receive and transmit
Data Sheet
29
V1.2, 2002-05
TC1775
Preliminary Data Link Operation Features: * * * * * * 11-byte transmit buffer Double buffered 11-byte receive buffer Support of In-Frame Response (IFR) types 1, 2, 3 Advanced interrupt handling for RX, TX, and error conditions All interrupt sources can be enabled/disabled individually Support of automatic IFR Transmission for IFR types 1 and 2 for 3-byte consolidated headers
Note: The SDLM module does not support the Pulse Width Modulation (PWM) data format.
Data Sheet
30
V1.2, 2002-05
TC1775
Preliminary Timer Units The TC1775 includes two timer units: - General Purpose Timer Unit (GPTU) - General Purpose Timer Array (GPTA) General Purpose Timer Unit Figure 9 shows a global view of all functional blocks of the General Purpose Timer Unit (GPTU) module.
IN 0 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 O UT0 O UT1 O UT2 O UT3 O UT4 O UT5 O UT6 O UT7 P ort C o ntro l IO 0 IO 1 IO 2 IO 3 IO 4 IO 5 IO 6 IO 7
C lo ck C o ntro l
fG PTU
P 13 .0 / G P T 0 P 13 .1 / G P T 1 P 13 .2 / G P T 2 P 13 .3 / G P T 3 P 13 .4 / G P T 4 P 13 .5 / G P T 5 P 13 .6 / G P T 6 P 13 .7 / G P T 7
M C B 04489
A d dre ss D e co de r SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 G P TU M o du le (K ern el)
In terru pt C o ntro l
Figure 9
General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. The GPTU communicates with the external world via eight inputs and eight outputs located at Port 13. The three timers of the GPTU module (T0, T1, and T2) can operate independently from each other, or can be combined: General Features: * * * * All timers are 32-bit precision timers with a maximum input frequency of fGPTU Events generated in T0 or T1 can be used to trigger actions in T2 Timer overflow or underflow in T2 can be used to clock either T0 or T1 T0 and T1 can be concatenated to form one 64-bit timer
Data Sheet
31
V1.2, 2002-05
TC1775
Preliminary Features of T0 and T1: * Each timer has a dedicated 32-bit reload register with automatic reload on overflow * Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers * Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events * Two input pins can define a count option Features of T2: * Count up or down is selectable * Operating modes: - Timer - Counter - Quadrature counter (incremental/phase encoded counter interface) * Options: - External start/stop, one-shot operation, timer clear on external event - Count direction control through software or an external event - Two 32-bit reload/capture registers * Reload modes: - Reload on overflow or underflow - Reload on external event: positive transition, negative transition, or both transitions * Capture modes: - Capture on external event: positive transition, negative transition, or both transitions - Capture and clear timer on external event: positive transition, negative transition, or both transitions * Can be split into two 16-bit counter/timers * Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions * Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins * T2 events are freely assignable to the service request nodes
Data Sheet
32
V1.2, 2002-05
TC1775
Preliminary General Purpose Timer Array Figure 10 shows a global block diagram of the General Purpose Timer Array (GPTA) implementation.
C lo ck C on trol
fG PTA
G PTA M odule K ernel C lo ck G e ne ra tio n U n it F ilte r & P res ca le r C e lls P ha se D iscrim ina tor Lo gic D igital P h as e L oc ke d Lo o p
IN 0 IN 1 IN 62 IN 63
IO 0 IO 1 IO 1 4 IO 1 5 IO 1 6 IO 1 7 IO 3 0 IO 3 1 P ort C on trol IO 3 2 IO 3 3 IO 4 6 IO 4 7 IO 4 8 IO 4 9 IO 6 2 IO 6 3
P 8 .0 P 8 .1 P 8 .14 P 8 .15 P 9 .0 P 9 .1 P 9 .14 P 9 .15 P 1 0 .0 P 1 0 .1 P 10 .14 P 10 .15 P 1 1 .0 P 1 1 .1 P 11 .14 P 11 .15
M C B 04490
A d dre ss D e co de r
D u ty C ycle M ea su rem en t
IO Sharing Unit with Emergency Shut-Off
AS0 AS1 A S 62 A S 63
S R 00 S R 01 In te rrup t C on trol S R 52 S R 53
S ig na l G en era tio n U nit G lob a l T im er C e lls G lo ba l T im ers L oc al Tim e r C e lls
O U T0 O U T1 O U T6 2 O U T6 3
A /D C on ve rter
P TIN 00 P TIN 01 P TIN 10 P TIN 11
In te rrup t C o ntro l U nit
Figure 10
GPTA Module Block Diagram
The GPTA module has 64 input lines and 64 output lines, which are connected with Port 8, Port 9, Port 10, and Port 11. The General Purpose Timer Array (GPTA) provides important digital signal filtering and timer support whose combination enables autonomous and complex functionalities. This architecture allows easy implementation and easy validation of any kind of timer functions.
Data Sheet
33
V1.2, 2002-05
TC1775
Preliminary The General Purpose Timer Array (GPTA) provides a set of hardware modules required for high speed digital signal processing: * Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. * Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. * Duty Cycle Measurement Cells (DCM) provide pulse width measurement capabilities. * A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal's period. * Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated "Global Timer Cells". * Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an event that occurred at an external port pin or at an internal FPC output. A GTC may be also used to control an external port pin with the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. * Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also logically tied together to drive a common external port pin with a complex signal waveform. LTCs -- enabled in Timer Mode or Capture Mode -- can be clocked or triggered by - A prescaled GPTA module clock, - An FPC, PDL, DCM, PLL, or GTC output signal line, - An external port pin. Some input lines driven by processor I/O pads may be shared by an LTC and a GTC to trigger their programmed operation simultaneously. The following list summarizes all blocks supported: Clock Generation Unit (GPTA) * Filter and Prescaler Cell (FPC): - Six independent units - Three operating modes (Prescaler, Delayed Debounce Filter, Immediate Debounce Filter) - fGPTA down-scaling capability - fGPTA/2 maximum input signal frequency in Filter Mode * Phase Discriminator Logic (PDL): - Two independent units - Two operating modes (2 and 3 sensor signals) - fGPTA/4 maximum input signal frequency in 2-sensor mode, fGPTA/6 maximum input signal frequency in 3-sensor mode * Duty Cycle Measurement (DCM): - Four independent units - 0 to 100% margin and time-out handling
Data Sheet
34
V1.2, 2002-05
TC1775
Preliminary - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency * Digital Phase Locked Loop (PLL): - One unit - Arbitrary multiplication factor between 1 and 65535 - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency GPTA Signal Generation Unit * Global Timers (GT): - Two independent units - Two operating modes (Free Running Timer and Reload Timer) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency * Global Timer Cell (GTC): - 32 independent units - Two operating modes (Capture, Compare and Capture after Compare) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency * Local Timer Cell (LTC): - 64 independent units - Three operating modes (Timer, Capture and Compare) - 16-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Interrupt Control Unit * 111 interrupt sources generating 54 service requests I/O Sharing Unit * Able to process lines from FPC, GTC, and LTC * Emergency function
Data Sheet
35
V1.2, 2002-05
TC1775
Preliminary Analog Digital Converters The two on-chip Analog-to-Digital Converter (ADC) modules of the TC1775 offer 8-bit, 10-bit, or 12-bit resolution including sample-and-hold functionality. The A/D converters operate using the method of the successive approximation. A multiplexer selects among up to 16 analog input channels for each ADC. Conversion requests are generated either under software control or by hardware. An automatic self-calibration adjusts the ADC modules to changing temperatures or process variations. Features: * * * * * * * * * * * * * * * * * * * 8-bit, 10-bit, 12-bit A/D conversion Successive approximation conversion method Fast conversion times: e.g. 10-bit conversion (without sample time): 5.05 s Total Unadjusted Error (TUE) of 2 LSB @ 10-bit resolution Integrated sample-and-hold functionality Sixteen analog input channels Dedicated control and status registers for each analog channel Powerful conversion request sources Selectable reference voltages for each channel Programmable sample and conversion timing schemes Limit checking Broken wire - short circuit detection Flexible service request generation Synchronization of the two on-chip A/D Converters Automatic control of external analog multiplexer Equidistant samples initiated by timer External trigger inputs for conversion requests Two external trigger inputs, connected with the General Purpose Timer Array (GPTA) Power reduction and clock control
Figure 11 shows a global view of the ADC module kernels with the module specific interface connections. Each of the ADC modules communicates with the external world via five digital I/O lines and sixteen analog inputs. Clock control, address decoding, and interrupt service request control are managed outside the ADC module kernel. Two trigger inputs and a synchronization bridge are used for internal control purposes.
Data Sheet
36
V1.2, 2002-05
TC1775
Preliminary
V A R E F 0 V S SA 0 V SSM V AG ND0 V DDA0 V DDM fADC0
P ort C on trol A d d res s D e co d er SR0 SR1 SR2 SR3 P T IN 0 0 P T IN 0 1 G PTA P T IN 1 0 P T IN 1 1 P ort C on trol ADC0 M o du le K ern e l A IN 0 A IN 1 P 12 .8 / A D 0 E X T IN 0 P 12 .9 / A D 0 E X T IN 1 P 12 .0 / AD0EM UX0 P 12 .1 / AD0EM UX1 P 12 .2 / AD0EM UX2 P 6.0 / A N 0 P 6.1 / A N 1
C lo ck C o ntro l
In terru pt C o ntro l
A IN 1 4 A IN 1 5 S yn chro n iz ation B rid g e
P 6.1 4 / A N 14 P 6.1 5 / A N 15
C lo ck C o ntro l
fADC1
A d d res s D e co d er SR0 SR1 SR2 SR3
ADC1 M o du le K ern e l
P 12 .6 / A D 1 E X T IN 0 P 12 .7 / A D 1 E X T IN 1 P 12 .3 / AD1EM UX0 P 12 .4 / AD1EM UX1 P 12 .5 / AD1EM UX2 P 7.0 / A N 1 6 P 7.1 / A N 1 7
A IN 0 A IN 1
In terru pt C o ntro l
A IN 1 4 A IN 1 5
P 7.1 4 / A N 30 P 7.1 5 / A N 31
V A G N D 1 V D D A1 V D D M V A R EF 1 V S SA 1 V S SM
M C B 04491
Figure 11
ADC0/ADC1 Modules with Interconnections
Data Sheet
37
V1.2, 2002-05
TC1775
Preliminary On-Chip Memories The memory system of the TC1775 provides the following memories: * Program Memory Unit (PMU) with - 8 Kbytes Boot ROM (BROM) - 32 Kbytes Code Scratch-Pad RAM (SPRAM) - 1 Kbyte Instruction Cache (ICACHE) * Data Memory Unit (DMU) with - 40 Kbytes Data Memory (SRAM) - Includes 8 Kbytes static RAM (SBSRAM) for standby operation using a battery * Peripheral Control Processor (PCP) with - 16 Kbytes Data Memory (PCODE) - 4 Kbytes Parameter RAM (PRAM)
Data Sheet
38
V1.2, 2002-05
TC1775
Preliminary Address Map Table 2 defines the specific segment oriented address blocks of the TC1775 with its address range, size, and PMU/DMU access view. Table 3 shows the block address map of memory segment 15 which includes the on-chip peripheral units. Table 2 TC1775 Block Address Map Size 2 GB Description Reserved DMU Acc. - via FPI DMU local via FPI PMU Acc.1) - PMU local cached non-cached via FPI via EBU or FPI via EBU via FPI
Seg- Address ment Range 0 to 7 0000 0000H - 7FFF FFFFH 8 9 10 8000 0000H - 8FFF FFFFH 9000 0000H - 9FFF FFFFH A000 0000H - AFFF FFFFH B000 0000H - BDFF FFFFH BE00 0000H - BEFF FFFFH 11 BF00 0000H - BFFF DFFFH
256 MB Reserved 256 MB Reserved 256 MB External Memory Space
224 MB External Memory Space mappable into segment 10 16 MB - External Emulator Space Reserved Boot ROM 4 Kbytes general purpose 4 Kbytes factory test support Local Code Scratch-Pad RAM (SPRAM) Reserved PMU Control Registers via FPI via FPI
BFFF E000H - 8 KB BFFF FFFFH C000 0000H - C000 7FFFH C000 8000H - C7FF FEFFH 32 KB -
PMU local
12
C7FF FF00H - 256 B C7FF FFFFH C800 0000H - CFFF FFFFH
PMU local
128 MB Reserved
Data Sheet
39
V1.2, 2002-05
TC1775
Preliminary Table 2 TC1775 Block Address Map (cont'd) Size 32 KB 8 KB 8 KB Description Local Data Memory (SRAM) Local Data Memory for standby operation (SBSRAM) SBSRAM mirrored SBSRAM mirrored SBSRAM mirrored Reserved DMU Registers non-cached DMU local via FPI DMU Acc. PMU Acc.1)
Seg- Address ment Range D000 0000H - D000 7FFFH D000 8000H - D000 9FFFH D000 A000H - D000 BFFFH
13
D000 C000H - 8 KB D000 DFFFH D000 E000H - D000 FFFFH D000 A000H - D7FF FEFFH 8 KB -
D7FF FF00H - 256 B D7FF FFFFH D800 0000H - DFFF FFFFH 14 E000 0000H - EFFF FFFFH
256 MB Reserved 256 MB External Peripheral and Data Memory Space via FPI not possible
Data Sheet
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V1.2, 2002-05
TC1775
Preliminary Table 2 TC1775 Block Address Map (cont'd) Size 16 KB 256 B - 4 KB - 16 KB - 12 x 256 B - Description On-Chip Peripherals & Ports PCP Registers Reserved PCP Parameter Memory (PRAM) Reserved PCP Code Memory (PCODE) Reserved CAN Module Reserved CPU Slave Interface Registers (CPS) Core SFRs + GPRs via FPI not possible non-cached DMU Acc. PMU Acc.1)
Seg- Address ment Range F000 0000H - F000 3EFFH F000 3F00H - F000 3FFFH F000 4000H - F000 FFFFH F001 0000H - F001 0FFFH F001 1000H - F001 FFFFH 15 F002 0000H - F002 3FFFH F002 4000H - F00F FFFFH F010 0000H - F010 0BFFH F010 0C00H - FFFE FEFFH
FFFE FF00H - 256 B FFFE FFFFH FFFF 0000H - FFFF FFFFH
1)
64 KB
The PMU can access external memory directly ("via EBU", only instruction accesses) or via the FPI Bus ("via FPI").
Data Sheet
41
V1.2, 2002-05
TC1775
Preliminary Table 3 SCU RTC BCU STM OCDS EBU - GPTU ASC0 ASC1 SSC0 SSC1 - GPTA - ADC0 ADC1 SDLM - P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 Block Address Map of Segment 15 Address Range F000 0000H - F000 00FFH F000 0100H - F000 01FFH F000 0200H - F000 02FFH F000 0300H - F000 03FFH F000 0400H - F000 04FFH F000 0500H - F000 05FFH F000 0600H - F000 06FFH F000 0700H - F000 07FFH Size 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 8 x 256 Bytes - 512 Bytes 512 Bytes 256 Bytes - 256 Bytes 256 Bytes 256 Bytes 256 Bytes System Control Unit Real Time Clock Bus Control Unit System Timer On-Chip Debug Support External Bus Unit Reserved General Purpose Timer Unit
Symbol Description
Async./Sync. Serial Interface 0 F000 0800H - F000 08FFH Async./Sync. Serial Interface 1 F000 0900H - F000 09FFH High-Speed Synchronous Serial Interface 0 High-Speed Synchronous Serial Interface 1 Reserved General Purpose Timer Array Reserved Analog-to-Digital Converter 0 Analog-to-Digital Converter 1 Serial Data Link Module Reserved Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 (no registers available) Port 7 (no registers available) Port 8 Port 9 F000 0A00H - F000 0AFFH F000 0B00H - F000 0BFFH F000 0C00H - F000 17FFH F000 1800H - F000 1FFFH F000 2000H - F000 21FFH F000 2200H - F000 23FFH F000 2400H - F000 25FFH F000 2600H - F000 26FFH F000 2700H - F000 27FFH F000 2800H - F000 28FFH F000 2900H - F000 29FFH F000 2A00H - F000 2AFFH F000 2B00H - F000 2BFFH
F000 2C00H - F000 2CFFH 256 Bytes F000 2D00H - F000 2DFFH 256 Bytes F000 2E00H - F000 2EFFH F000 2F00H - F000 2FFFH F000 3000H - F000 30FFH F000 3100H - F000 31FFH
42
256 Bytes 256 Bytes 256 Bytes 256 Bytes
V1.2, 2002-05
Data Sheet
TC1775
Preliminary Table 3 P10 P11 P12 P13 - PCP Block Address Map of Segment 15 (cont'd) Address Range F000 3200H - F000 32FFH F000 3300H - F000 33FFH F000 3400H - F000 34FFH F000 3500H - F000 35FFH F000 3600H - F000 3EFFH F000 3F00H - F000 3FFFH F000 4000H - F000 FFFFH F001 0000H - F001 0FFFH F001 1000H - F001 FFFFH F002 0000H - F002 3FFFH F002 4000H - F00F FFFFH F010 0000H - F010 0BFFH Size 256 Bytes 256 Bytes 256 Bytes 256 Bytes - 256 Bytes - 4 Kbytes - 16 Kbytes - 12 x 256 Bytes Port 10 Port 11 Port 12 Port 13 Reserved PCP Registers Reserved PCP Data Memory (PRAM) Reserved PCP Code Memory (PCODE) - CAN1) - CPU Reserved Controller Area Network Module Reserved Slave Interface Registers (CPS) Reserved Memory Protection Registers Reserved Core Special Function Registers (CSFRs) General Purpose Register (GPRs)
1)
Symbol Description
F010 0C00H - FFFE FEFFH - FFFE FF00H - FFFE FFFFH 256 Bytes FFFF 0000H - FFFF BFFFH - FFFF C000H - FFFF EFFFH 12 Kbytes FFFF F000H - FFFF FCFFH - FFFF FE00H - FFFF FEFFH 256 Bytes FFFF FF00H - FFFF FFFFH 256 Bytes
Core Debug Register (OCDS) FFFF FD00H - FFFF FDFFH 256 Bytes
Access to unused address regions within this peripheral unit don't generate a bus error.
Data Sheet
43
V1.2, 2002-05
TC1775
Preliminary Memory Protection System The TC1775 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the kinds of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. There are two Memory Protection Register Sets in the TC1775, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these is the set currently in use by the CPU. Because the TC1775 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive particular protection modes. Each of the Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each contains register pairs which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes which apply to the specified range.
Data Sheet
44
V1.2, 2002-05
TC1775
Preliminary On-Chip FPI Bus The FPI Bus interconnects the functional units of the TC1775, such as the CPU and on-chip peripheral components. The FPI Bus also interconnects the TC1775 to external components by way of the External Bus Controller Unit (EBU). The FPI Bus is designed to be quick to acquire by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications. The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 160 Mbyte/s can be achieved with a 40 MHz bus clock and 32-bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Features: * * * * * * Supports multiple bus masters Supports demultiplexed address/data operation Address and data buses are 32 bits wide Data transfer types include 8-, 16-, and 32-bit sizes Single- and multiple-data transfers per bus acquisition cycle Designed to minimize EMI and power consumption
Data Sheet
45
V1.2, 2002-05
TC1775
Preliminary External Bus Unit The External Bus Unit (EBU) of the TC1775 is the interface between external memories and peripheral units and the internal memories and peripheral units. The basic structure of the EBU is shown in Figure 12.
PMU
w ith o n -ch ip P ro g ra m M e m o ry
B u rst M o de Instru ction F etch e s
P o rt 4
C o n tro l Lin es A [2 5:16 ] an d C h ip S e le ct A [1 5:0]
P o rt 3
T riC o re CPU
F P I B us
EBU
P o rt 2
P o rt 1
A D [31 :1 6 ]
DMU
w ith o n -ch ip D a ta M e m o ry
P o rt 0 T o P e riph era l U nits an d P C P
A D [1 5:0 ]
M C A04753
Figure 12
EBU Structure and Interfaces
The EBU is primarily used for the following two operations: * Communication with external memories or peripheral units via the FPI Bus * Instruction fetches from the PMU to external Burst Flash program memories The EBU controls all transactions required for these two operations and in particular handles the arbitration between these two tasks. The types of external devices/bus modes controlled by the EBU are: * * * * * INTEL style peripherals (separate RD and WR signals) ROMs, EPROMs Static RAMs Demultiplexed A/D bus Multiplexed A/D bus - Burst Mode Flash Memories (ROM) Note: Instruction fetches of the PMU from external Burst Flash program memories are only possible with 32-bit data bus width.
The PMU controls accesses to external code memories. It especially supports:
Data Sheet
46
V1.2, 2002-05
TC1775
Preliminary Peripheral Control Processor The Peripheral Control Processor (PCP) performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor's first line of defense as an interrupt-handling engine. The PCP can offload the CPU from having to service time-critical interrupts. This provides many benefits, including: * Avoiding large interrupt-driven task context-switching latencies in the host processor * Lessening the cost of interrupts in terms of processor register and memory overhead * Improving the responsiveness of interrupt service routines to data-capture and datatransfer operations * Easing the implementation of multitasking operating systems. The PCP has an architecture that efficiently supports DMA type transactions to and from arbitrary devices and memory addresses within the TC1775 and also has reasonable stand alone computational capabilities. The PCP is made up of several modular blocks as follows: * * * * * * PCP Processor Core Code Memory (PCODE) Parameter Memory (PRAM) PCP Interrupt Control Unit (PICU) PCP Service Request Nodes (PSRN) System bus interface to the FPI Bus
The PCP is fully interrupt-driven, meaning it is only activated through service requests; there is no main program running in the background as with a conventional processor.
Data Sheet
47
V1.2, 2002-05
TC1775
Preliminary
Code M e m o ry PCO DE
P a ram e ter M em ory PRAM
PCP P ro ce ss or C o re
F P I-Interfa ce
P C P S e rvice R eq . N o de s PSRNs
P C P In terru pt C on trol U n it P IC U
FPI Bus
P C P Inte rrup t A rb itra tio n B u s C P U Inte rrup t A rb itra tio n B u s
M C B 04784
Figure 13 Table 4
PCP Block Diagram PCP Instruction Set Overview Description Efficient DMA channel implementation Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Add, subtract, compare and complement Divide and multiply And, Or, Exclusive Or, Negate Shift right or left, rotate right or left, prioritize Set, clear, insert and test bits Jump conditionally, jump long, exit No operation, Debug
Instruction Group DMA primitives Load/Store
Arithmetic Divide/Multiply Logical Shift Bit Manipulation Flow Control Miscellaneous
Data Sheet
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V1.2, 2002-05
TC1775
Preliminary System Timer The STM within the TC1775 is designed for global system timing applications requiring both high precision and long range. The STM provides the following features: * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Driven by clock fSTM (identical with the system clock fSYS) Counting begins at power-on reset Continuous operation is not affected by any reset condition except power-on reset
The STM is an upward counter, running with the system clock frequency fSYS. It is enabled per default after reset, and immediately starts counting up. Other than via reset, it is not possible to affect the contents of the timer during normal operation of the application, it can only be read, but not written to. Depending on the implementation of the clock control of the STM, the timer can optionally be disabled or suspended for power-saving and debugging purposes via a clock control register. The maximum clock period is 256 x 1/fSTM. At fSTM = 40 MHz, for example, the STM counts 57.1 years before overflowing. Thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing.
STM Module
fSTM
PORST
55
47
39
31
23
15
7
56-Bit System Timer
Enable/ Clock Disable Control
00H 00H TIM5
CAP TIM6
Address Decoder
TIM4 TIM3 TIM2 TIM1 TIM0
MCA04795
Figure 14
Data Sheet
Block Diagram of the STM Module
49 V1.2, 2002-05
TC1775
Preliminary Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1775 in a user-specified time period. When enabled, the WDT will cause the TC1775 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1775 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. In addition to this standard "Watchdog" function, the WDT incorporates the EndInit feature and monitors its modifications. A system-wide line is connected to the ENDINIT bit implemented in a WDT control register, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). A further enhancement in the TC1775's Watchdog Timer is its reset prewarning operation. Instead of immediately resetting the device on the detection of an error, as known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI) to the CPU before finally resetting the device at a specified time period later. This gives the CPU a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. Features: * 16-bit Watchdog counter * Selectable input frequency: fSYS/256 or fSYS/16384 * 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes * Incorporation of the ENDINIT bit and monitoring of its modifications * Sophisticated password access mechanism with fixed and user-definable password fields * Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and limited. * Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation. * Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. * Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. * Double Reset Detection: If a Watchdog induced reset occurs twice without a proper access to its control register in between, a severe system malfunction is assumed and the TC1775 is held in reset until a power-on reset. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed.
Data Sheet
50
V1.2, 2002-05
TC1775
Preliminary * Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. Real Time Clock Figure 15 shows a global view of all functional blocks oft he RTC interface.
X TA L3 32 kH z X TA L4 SCU RTC O sc illato r
fR TC_CO UN T f S YS
M o de _ S ele ct RTC M o du le (K ern el) R TC IN T In terru pt C o ntro l
A dd res s D ec od er
M C B 04808
Figure 15
Block Diagram of the RTC Interface
The Real Time Clock (RTC) module is an independent timer chain that counts time ticks. The base frequency of the RTC can be programmed via a reload counter. The RTC can work asynchronously with the system frequency, and is optimized on low power consumption. Features: * * * * On-chip 32.768 kHz oscillator for counting current time and date Cyclic time-based interrupts Alarm interrupt for wake-up on a defined time 48-bit timer for long-term measurements
Data Sheet
51
V1.2, 2002-05
TC1775
Preliminary System Control Unit The System Control Unit (SCU) of the TC1775 handles the system control tasks. All these system functions are tightly coupled, thus, they are conveniently handled by one unit, the SCU. The system tasks of the SCU are: * Reset Control - Generation of all internal reset signals - Generation of external HDRST reset signal * PLL Control - PLL_CLC Clock Control Register * Power Management Control - Enabling of several power-down modes - Control of the PLL in power-down modes * Watchdog Timer * Port 5 Trace Control * Device Identification
Data Sheet
52
V1.2, 2002-05
TC1775
Preliminary Interrupt System An interrupt request can be serviced either by the CPU or by the Peripheral Control Processor (PCP). These units are called "Service Providers". Interrupt requests are called "Service Requests" rather than "Interrupt Requests" in this document because they can be serviced by either of the Service Providers. Each peripheral in the TC1775 can generate service requests. Additionally, the Bus Control Unit, the Debug Unit, the PCP, and even the CPU itself can generate service requests to either of the two Service Providers. As shown in Figure 16, each TC1775 unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where "mod" is the identifier of the service requesting unit and "x" an optional index. Two buses connect the SRNs with two Interrupt Control Units, which handle interrupt arbitration among competing interrupt service requests, as follows: * The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus. * The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP and administers the PCP Interrupt Arbitration Bus. Units, which can generate service requests are: - - - - - - - - - - - - General Purpose Timer Unit (GPTU) with 8 SRNs General Purpose Timer Array (GPTA) with 54 SRNs Two High-Speed Synchronous Serial Interfaces (SSC0/SSC1) with 3 SRNs each Two Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) with 4 SRNs each TwinCAN controller with 8 SRNs Serial Data Link Module (SDLM) with 2 SRNs Two Analog/Digital Converters (ADC0/ADC1) with 4 SRNs each Real Time Clock (RTC) with 1 SRN Bus Control Unit (BCU) with 1 SRN Peripheral Control Processor (PCP) with 4 SRNs Central Processing Unit (CPU) with 4 SRNs Debug Unit (OCDS) with 1 SRN
The PCP can make service requests directly to itself (via the PICU), or it can make service requests to the CPU. The Debug Unit can generate service requests to the PCP or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can make service requests to the PCP. The CPU Service Request Nodes are activated through software. External interrupt inputs in TC1775 are available using the input pins connected to the General-Purpose Timer Unit (GPTU). Each of the eight GPTU I/O pins can be used as an external interrupt input, using the Service Request Nodes of the GPTU module. In addition, such an external interrupt input can also trigger a timer function.
Data Sheet
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V1.2, 2002-05
TC1775
Preliminary
PCP In te rru pt A rbitration B u s S erv ic e R e q ue stors G P TU G P TA SSC0 SSC1 ASC0 ASC1 CAN SDLM ADC0 ADC1 RTC BCU 8 54 3 3 4 4 8 2 4 4 1 1 S e rvice R e q ue st N od e s 8 SRNs 54 S R N s 3 SRNs 3 SRNs 4 SRNs 4 SRNs 8 SRNs 2 SRNs 4 SRNs 4 SRNs 1 SRN 1 SRN
CPU In terru pt A rbitration B u s In te rru pt C o ntro l U nits In terru pt S e rvice P ro vid ers Int. A ck . CCPN PCP 2 2
8 8 54 54 3 3 3 3 4 4 4 4 8 8 2 2 4 4 4 4 1 1 1 1 P IP N IC U In t. R eq . 4 4 4 SRNs 4 1 1 1 SRNs 1 2 2 In t. R eq . P IP N PIC U 2 SRNs 2 SRNs
D e bu g U nit
S o ftw a re Inte rrup t
C PU Int. A ck . CCPN
M C B 04779
Figure 16
Block Diagram of the TC1775 Interrupt System
Note: Depending on the selected system frequency fSYS, the number of clocks for interrupt arbitration cycles must be selected as follows: fSYS 30 MHz: ICR.CONECYC = 1 fSYS > 30 MHz: ICR.CONECYC = 0
Data Sheet
54
V1.2, 2002-05
TC1775
Preliminary Boot Options The TC1775 booting schemes provides a number of different boot options for the start of code execution. Table 5 shows the boot options available in the TC1775. Table 5 Boot Selections Type of Boot Start from Boot ROM Boot Source Initial PC Value Boot ROM BFFF FFFCH
OCDSE BRKIN CFG CFG [3] [2:0] 1 1 X 000B 001B 010B 0 1 0 1 X 100B 100B 101B 101B 011B 110B 111B 100B or 101B
External memory as slave directly via EBU External memory as master directly via EBU External memory as slave via FPI Bus External memory as master via FPI Bus
External Memory (cached)
A000 0000H
Reserved; don't use these combinations;
0
1
0 1
Go to halt with EBU enabled as slave Go to halt with EBU enabled as master Go to halt with EBU disabled Go to external emulator space Tri-state chip (deep sleep)
-
-
all other combinations 0 1 0 0 don't care don't care
- -
BE00 0000H -
Data Sheet
55
V1.2, 2002-05
TC1775
Preliminary Power Management System The TC1775 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are four power management modes: * * * * Run Mode Idle Mode Sleep Mode Deep Sleep Mode
Table 6 describes these features of the power management modes. Table 6 Mode Run Idle Power Management Mode Summary Description The system is fully operational. All clocks and peripherals are enabled, as determined by software. The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. The system clock continues to be distributed only to those peripherals programmed to operate in Sleep Mode. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine. The system clock is shut off; only an external signal will restart the system. Entering this state requires an orderly shut-down controlled by the Power Management State Machine (PMSM).
Sleep
Deep Sleep
Data Sheet
56
V1.2, 2002-05
TC1775
Preliminary On-Chip Debug Support The On-Chip Debug Support of the TC1775 consists of four building blocks: * OCDS module in the TriCore CPU - On-chip breakpoint hardware - Support of an external break signal * OCDS module in the PCP - Special DEBUG instruction for program execution tracing * Trace module of the TriCore - Outputs 16 bits per cycle with pipeline status information, PC bus information, and breakpoint qualification information * Debugger Interface (Cerberus) - Provided for debug purposes of emulation tool vendors - Accessible through a JTAG standard interface with dedicated JTAG port pins Figure 17 shows a basic block diagram of the building blocks.
FPI Bus
B R K IN PCP SC U T rac e C o ntro l BRKOUT
Port 5
16
T R A C E [15 :0 ]
TriCore CPU O CDS OCDSE
TDI TDO C erberus & JTA G TM S TCK TRST
M C B 04810
JT A G I/O Line s
Figure 17
Data Sheet
OCDS Support Basic Block Diagram
57 V1.2, 2002-05
TC1775
Preliminary Clock Generation Unit The Clock Generation Unit (CGU) in the TC1775, shown in Figure 18, consists of an oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it looses its lock on the external clock. In general, the CGU is controlled through the System Control Unit (SCU) module of the TC1775.
Clock Generation Unit CGU XTAL1 Oscillator fOSC Circuit XTAL2 N Divider PLL 1
&
1
Phase Detect.
VCO
fVCO MUX
0
K Divider
MUX 0
System_ CLK
fSYS
Lock Detector
CLKSEL[2:0] BYPASS
OSC_OK
PLL Locked
Deep NDIV[2:0] Sleep
VCO_ KDIV[2:0] PLL_ BYPASS BYPASS Register PLL_CLC
MCA04713
System Control Unit SCU
Figure 18
Clock Generation Unit Block Diagram
Besides the two XTAL pins for the oscillator, input pins CLKSEL[2:0] and BYPASS are used for configuration of the clock generation unit. These inputs are checked by the SCU which generates the appropriate control signals and latches the state of these signals into register PLL_CLC.
Data Sheet
58
V1.2, 2002-05
TC1775
Preliminary PLL Operation The fVCO clock of the PLL has a frequency which is a multiple of the externally applied clock fOSC. The factor for this is controlled through the value N applied to the divider in the feedback path. N is defined through three PLL configuration inputs CLKSEL[2:0]. Table 7 CLKSEL[2:0] 000B 001B 010B 011B 100B 101B 110B 111B Input Frequencies and N Factor for fVCO N-Factor 8 9 10 11 12 13 14 15
fVCO = 150 MHz
18.75 16.67 15 13.64 12.5 11.54 10.71 10
fVCO = 160 MHz
20 17.76 16 14.55 13.33 12.31 11.43 10.67
fVCO = 200 MHz
25 22.22 20 18.18 16.67 15.38 14.29 13.33
Shaded combinations should not be used because the maximum oscillator frequency of 16 MHz is exceeded.
The K-Divider is a software controlled divider. Table 8 lists the possible values for K and the resulting division factor. Table 8 Selected Factor 2 4 52) 6 8 9
2)
Output Frequencies fSYS Derived from Various Output Factors K-Factor KDIV 000B 010B 011B 100B 101B 110B 111B 001B
fSYS1) fVCO =
150 MHz 75 37.5 30 24.5 18.75 16.67 15 9.38
fVCO =
160 MHz 80 40 32 26.67 20 17.78 16 10
fVCO =
200 MHz 100 50 40 33.33 25 22.22 20 12.5
Duty Cycle [%] 50 50 40 50 50 44 50 50
10 16
Shaded combinations cannot not be used because the maximum system clock frequency of 40 MHz is exceeded.
1)
Depending on the selected system frequency fSYS, the number of clocks for interrupt arbitration cycles must be selected as follows: fSYS 30 MHz: ICR.CONECYC = 1, fSYS > 30 MHz: ICR.CONECYC = 0. These odd K-Factors should not be used (not tested because of the unsymmetrical duty cycle).
2)
Data Sheet
59
V1.2, 2002-05
TC1775
Preliminary Recommended Oscillator Circuits
V DDO SC V DDOSC
X TA L 1 1 -1 6 M Hz TC 1775 M ain O scillator X TA L 2
E xterna l C lock S ig n a l
XTAL1 TC1775 M ain O scillator XTAL2
C1
C2 V SSOSC V SSO SC
V DD
M C S0 47 14
X T A L3 3 2 .7 6 8 kH z TC1775 R TC O scillator X T A L4
C1
C2 V SS
M C S 04 71 6
Figure 19
Oscillator Circuitries
For the main oscillator of the TC1775 the following external passive components are recommended: - Crystal: max. 16 MHz - C1, C2: 10 pF A block capacitor between VDDOSC and VSSOSC is recommended, too. For the RTC oscillator of the TC1775 the following external passive components are recommended: - Crystal: 32.768 kHz - C1, C2: 12 pF Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier.
Data Sheet 60 V1.2, 2002-05
TC1775
Preliminary Power Supply Figure 20 shows the TC1775's power supply concept, where certain logic modules are individually supplied with power. This concept improves the EMI behavior by reduction of the noise cross coupling. Also the operation margin is improved in sensitive modules like the A/D converter by noise reduction.
V D D A0
(2 .5 V )
V DDM
(5 V )
V DDSC
(5 V )
V D D A1
(2 .5 V )
V SSA0
V S SM
V S SS C
V SSA1
TC 1775 S h ort C irc uit / B ro ke n W ire L og ic S ho rt C ircu it / B rok en W ire Lo g ic
ADC0
ADC1
C o n tro l L o gic
C o ntrol Lo g ic
PCP M em o ry
DM U
PMU
G P IO P o rts (P 8-P 13 )
EBU P o rts (P 0-P 5)
CPU & C o ntrol & P e rip he rals
PLL
OSC
V DDSRAM
(2 .5 V )
V DDSB
(2 .5 V )
V DDP813
(3.3 - 5 V )
V DDP05
(2.5 V )
V DD
(2 .5 V )
V D D PL L V D D O S C
(2 .5 V ) (2.5 V )
V SS
V SS
V SS
V SS
V SS
V SSPLL V DDO SC
M C D 04878
Figure 20
TC1775 Power Supply Concept
Data Sheet
61
V1.2, 2002-05
TC1775
Preliminary Ports Power Supply The TC1775's port power supply concept is shown in Figure 21. The ports assigned with the External Bus Unit (EBU) are in a separate power supply group for 2.5 V nominal operating voltage. The general purpose input/outputs (GPIOs) except the EBU provide 3.3 to 5 V input/output acceptance and drive characteristics.
V DDP05
(2.5 V )
V DDP813
(3 .3 - 5 V )
V SS
P o rts 0 to 5 (P ad s) & S ch m itt T rigg er
P o rts 8 to 1 3 (P ad s) & S ch m itt T rig g er
V DD
(2 .5 V )
P o rt Lo gic
M C A 04752
Figure 21
Ports Power Supply Concept
Power-up Sequence During Power-up the reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the Power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the difference between VDDP813 and VDDI (i.e. VDDP813 - VDDI) never drops below -0.3 V (VDDI = VDD and VDDP05). Power Loss If VDDP813 is dropping below VDDI, external circuitry in the power supply has to ensure, that VDDI is also limited to the same level. If VDDI is dropping below the operating range, VDDP813 may stay active. Powering Down During powering down (falling of the supply voltages from their regular operating values to zero), it has to be ensured, that the difference between VDDP813 and VDDI (VDDP813 - VDDI) never drops below -0.3 V.
Data Sheet
62
V1.2, 2002-05
TC1775
Preliminary Identification Register Values Table 9 Short Name PMU_ID DMU_ID SCU_ID MANID CHIPID RTID RTC_ID BCU_ID STM_ID JPD_ID EBU_ID GPTU_ID ASC0_ID ASC1_ID SSC0_ID SSC1_ID GPTA_ID ADC0_ID ADC1_ID SDLM_ID PCP_ID CAN_ID CPU_ID TC1775 Identification Registers Address C7FF FF08H D7FF FF08H F000 0008H F000 0070H F000 0074H F000 0078H F000 0108H F000 0208H F000 0308H F000 0408H F000 0508H F000 0708H F000 0808H F000 0908H F000 0A08H F000 0B08H F000 1808H F000 2208H F000 2408H F000 2608H F000 3F08H F010 0008H FFFE FF08H Value 0006 C002H 0007 C002H 0003 C002H 0000 1820H 0000 8002H 0000 0000H 0000 5A01H 0000 6A05H 0000 C002H 0000 6301H 0005 C002H (BA11-Step) 0005 C003H (BA21-Step) 0001 C002H 0000 4401H 0000 4401H 0000 4503H 0000 4503H 0002 C001H 0000 3101H 0000 3101H 0000 4202H 000D C001H 0000 4110H 0000 0202H
Data Sheet
63
V1.2, 2002-05
TC1775
Preliminary Parameter Interpretation The parameters listed on the following pages partly represent the characteristics of the TC1775 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the TC1775 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the TC1775. Pin Classes The TC1775 has three classes of digital I/O pins: - Class A pins, which are 3.3 V to 5 V nominal voltage pins - Class B pins, which are 2.5 V nominal voltage pins (input tolerant for 3.3 V) - Class C pins, which are 2.5 V nominal voltage pins only Table 10 shows the assignments of all digital I/O pins to pin classes and to VDD power supply pins. Table 10 Pins Port 8 to Port 13 CLKSEL[2:0], BYPASS, CFG[3:0], HDRST Port 0 to 5 TRST, TCK, TDI, TDO, TMS, ODCSE, BRKIN, BRKOUT, NMI, PORST, CLKOUT, CLKIN TESTMODE Core supply, no pins assigned Assignments of Digital Pins to Pin Classes and Power Supply Pins Pin Classes Power Supply Class A VDDP813 (nominal 3.0 to 5.25 V) Class B (nominal 2.5 V, 3.3 V tolerant)
VSS
VDDP05
(nominal 2.5 V)
XTAL1, XTAL2, XTAL3, XTAL4
Class C (nominal 2.5 V)
VDD, VDDSRAM, VDDSB VDDPLL VDDOSC
VSSPLL VSSOSC
Data Sheet
64
V1.2, 2002-05
TC1775
Preliminary Absolute Maximum Ratings Parameter Ambient temperature Symbol -40 -65 - -0.5 -0.5 -0.5 Limit Values min. max. 125 150 150 6.2 3.25 3.25 Unit Notes under bias - under bias see Table 10 - -
TA TA Storage temperature Junction temperature TJ Voltage on Class A power supply VDD pins with respect to VSS Voltage on Class B and C power VDD supply pins with respect to VSS Voltage on power supply pins VDD
"no pins assigned" with respect to VSS Voltage on any Class A input pin VIN with respect to VSS Voltage on any Class B input pin VIN with respect to VSS Voltage on any Class C input pin VIN with respect to VSS Input current on any pin during overload condition
C C C
V V V
-0.5 -0.5 -0.5 -10 -
VDD + 0.5 V
3.7 V V mA mA
- - - - -
VDDOSC
+ 0.5 10 |100|
IIN
Absolute sum of all input currents IIN during overload condition
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
65
V1.2, 2002-05
TC1775
Preliminary Package Parameters (P-BGA-329) Parameter Power dissipation Thermal resistance Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1775. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. Parameter Digital supply voltage
1)
Symbol
Limit Values min. max. 1 23 - -
Unit Notes W -
PDISS RTHA
K/W Chip to ambient
Symbol
Limit Values min. max. 5.25 2.75 2.75 2.75 0 -40 2.25 4.5 4 +125 2.75 5.25
Unit Notes V V V V V Class A pins CPU Core and Class B pins Class C pins - - - - -
4)
VDDP813 3.0 VDD2) 2.3 VDDOSC VDDSB3) VSS TA VDDA VDDM VAREF VAGND VAIN fSYS IOV ISC
|IOV| + |ISC|
2.3 2.25
Digital ground voltage Ambient temperature under bias Analog supply voltages Analog reference voltage Analog ground voltage Analog input voltage CPU clock Overload current Short circuit current Absolute sum of overload + short circuit currents External load capacitance
Data Sheet
C
V V V V V mA mA mA pF
VDDM +
0.05
VSSA 0.05
VSSA +
0.05
5)
VAGND
- -10 -10 - -
66
VAREF
40 10 10 |50| 50
-
6)7)8) 3)4)9) 7)
MHz -
CL
-
V1.2, 2002-05
TC1775
Preliminary
1)
Digital supply voltages applied to the TC1775 must be static regulated voltages which allow a typical voltage swing of 10%. This VDD specification is applicable for the power supply pins: VDD, VDDOSC, VDDPLL, VDDSRAM, VDDP05, and VDDSB. In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be kept at the same voltage level during normal operating mode. This condition is typically achieved by generating the 2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if a separate stand-by power supply VDDSB is used. The minimum voltage at pin VDDSB during TC1775 power down mode is 1.8 V in order to keep the contents of SBRAM valid. The core power supply VDD must be below the standby power supply VDD < VDDSB + 0.3 V. The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range. The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Not 100% tested, guaranteed by design and characterization. Applicable for analog inputs. Applicable for digital inputs.
2)
3)
4)
5)
6)
7) 8) 9)
Data Sheet
67
V1.2, 2002-05
TC1775
Preliminary DC Characteristics Input/Output DC-Characteristics VSS = 0 V; TA = -40 C to +125 C; Parameter1) Symbol Limit Values min. Class A Pins (VDDP813 = 3.0 to 5.25 V) Output low voltage2) max. Unit Test Conditions
VOL CC
-
0.45
V
VDDP813
Output high voltage2) VOH CC 0.7 x - V
0.2 x
V
VDDP813
V
Input low voltage5)
VIL
SR
-0.5
0.8 0.43 x 0.2 x
V V V
IOL = 2.4 mA3) IOL = 600 A4) VDDP813 = 4.5 to 5.25 V IOL = 2.4 mA IOL = 600 A4) VDDP813 = 3.0 to 4.49 V IOH = -2.4 mA IOH = -600 A4) VDDP813 = 4.5 to 5.25 V IOH = -2.4 mA IOH = -600 A4) VDDP813 = 3.0 to 4.49 V VDDP813 = 4.5 to 5.25 V
(TTL)
VDDP813 VDDP813 VDDP813 V
+ 0.5 V 10 - - 120
VDDP813 = 4.5 to 5.25 V
(CMOS)
VDDP813 = 3.0 to 4.49 V
(CMOS)
Input high voltage5)
VIH
SR
2.0 0.73 x
VDDP813 = 4.5 to 5.25 V
(TTL)
VDDP813
Pull-up current6) Pull-down current7)
VDDP813 = 3.0 to 5.25 V
(CMOS)
IPUH IPUL IPDL IPDH
CC CC CC CC
- -120 10 -
A A A A
VOUT = VDDP813 - 0.02 V VOUT = 0.5 x VDDP813 VOUT = 0.02 V VOUT = 0.5 x VDDP813
Data Sheet
68
V1.2, 2002-05
TC1775
Preliminary Input/Output DC-Characteristics (cont'd) VSS = 0 V; TA = -40 C to +125 C; Parameter1) Symbol Limit Values min. Class B Pins (VDDP05 = 2.30 to 2.75 V) Output low voltage max. Unit Test Conditions
VOL CC
-
0.2 x 0.45
V
VDDP05
- - 3.7 V V V V
IOL = 2.4 mA IOL = 600 A IOH = -2.4 mA IOH = -600 A
- -
Output high voltage
VOH CC
0.7 x 0.9 x
VDDP05 VDDP05
Input high voltage Input low voltage Pull-up current6) Pull-down current7)
VIH VIL IPUH IPUL IPDL IPDH
SR SR CC CC CC CC
0.7 x -0.5 - -60 10 -
VDDP05
0.2 x 10 - - 60
VDDP05
A A A A
VOUT = VDDP05 - 0.02 V VOUT = 0.5 x VDDP05 VOUT = 0.02 V VOUT = 0.5 x VDDP05
Class A and B Pins Input Hysteresis HYS CC 0.065 x - V nA mA TTL and CMOS9) 0 V < VIN < VDDPx8)
12)9)
VDDPx
8)
Input leakage current IOZ2 CC (Digital I/O) Peak short-circuit current Peak back-drive current (per digital pin) Peak time & period time10)11) SR
-
500 20
ISCBDpeak -
Data Sheet
69
V1.2, 2002-05
TC1775
Preliminary Input/Output DC-Characteristics (cont'd) VSS = 0 V; TA = -40 C to +125 C; Parameter1) Symbol Limit Values min. Constant short-circuit ISCBDcons - SR current Constant back-drive current (per digital pin) Pin capacitance9) (Digital I/O) max. Unit Test Conditions mA
12)9)
10
CIO
CC
-
10
pF
f = 1 MHz TA = 25 C
Class C Pins (VDDOSC = 2.30 to 2.75 V), see Page 76
1)
All Class A pins of the TC1775 are equipped with Low-Noise output drivers, which significantly improve the device's EMI performance. These Low-Noise drivers deliver their maximum current only until the respective target output level is reached. After that the output current is reduced. This results in an increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current, which is specified in column "Test Conditions", is delivered in any case. This specification is not valid for outputs of GPIO lines, which are switched to open drain mode. In open drain mode the output will float and the voltage results from the external circuitry. Output drivers in high current mode. Condition for output driver in dynamic current mode & low current mode - guaranteed by design characterization. Input characteristics can be switched between TTL and CMOS via register Px_PICON except for dedicated pins which have CMOS input characteristics. The maximum current can be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. In case of Class B pins VDDx = VDDP05. In case of Class A pins VDDx = VDDP813. Guaranteed by design characterization. The max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 mA and the peak period equivalent of 10 mA constant-short-circuit current resp. 10 mA constant-back-drive current. The integral of ISCBDpeak over the peak period is thus limited to 10 mA (provided: ISCBDpeak 20 mA). To be defined for Class B pads. Short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the specified operating range (i.e. VSCBD > VDDPx + 0.5 V or VSCBD < VSS - 0.5 V) or a short circuit condition occurs on the respective pin. The absolute sum of input ISCBD and IOV currents on all port pins must not exceed 100 mA at any time. The supply voltage (VDDPx and VSS) must remain within the specified limits. Under shortcircuit conditions the corresponding pin is not ready for use. In case of Class B pins VDDx = VDDP05. In case of Class A pins VDDx = VDDP813.
2)
3) 4)
5)
6) 7) 8) 9) 10)
11) 12)
Data Sheet
70
V1.2, 2002-05
TC1775
Preliminary Pull-Up/Pull-Down Characteristics
Pull-up 700 A 700 A Pull-down Best Case
I
600 Best Case 500 400 Nominal 300 200 100 0 0
I
600 500 400 300 200 100 0 0
Nominal
Worst Case
Worst Case
1
2
3
4
5V6
1
2
3
4
5V6
V
V
MCD05235
Figure 22
Pull-Up/Pull-Down Characteristics of Class A Pins
Data Sheet
71
V1.2, 2002-05
TC1775
Preliminary
Pull-up 250 A 250 A Best Case 200
Pull-down
I
I
200 Best Case
150 Nominal
150 Nominal
100 Worst Case 50
100
50
Worst Case
0 0
0.5
1
1.5
2
2.5 V 3
0 0
0.5
1
1.5
2
2.5 V 3
V
V
MCD05236
Figure 23
Pull-Up/Pull-Down Characteristics of Class B Pins
Note: The pull-up/pull-down characteristics as shown in Figure 22 and Figure 23 are guaranteed by design characterization.
Data Sheet
72
V1.2, 2002-05
TC1775
Preliminary AD Converter Characteristics TA = -40 C to +125 C; VSS = 0 V;
Parameter Analog supply voltages Symbol min. Limit Values typ. 2.5 5 - - - max. 2.75 5.25 V V V V V V V
1)
Unit
Test Conditions
VDDAx SR VDDM SR VDDSC SR
2.25 4.5
- -
2) 3)
VDDM 0.05 -0.1 4
VDDM +
0.05 0.1
Analog ground voltage
VSSAx SR
Analog reference voltage VAREFx SR Analog reference ground VAGNDx SR Analog input voltage range Internal ADC clock
VDDM +
0.05
VSSAx - -
0.05
VSSAx +
0.05
4)
VAIN SR fANA
VAGNDx -
0.5 - - -
VAREFx
2
-
MHz - -
Power-up calibration time tPUC
3328 x (3 + s CON.CPS) x tBC s s s s s LSB LSB LSB mA mA mA mA mA mA
Sample time
tS
CC
(3 + CON.CPS) x (CHCONn.STC + 2) x tBC 6 x tBC - -
5)
Conversion time
tC
CC
tS + (30 + CON.CPS x 4) x tBC + 2 x tDIV tS + (36 + CON.CPS x 4) x tBC + 2 x tDIV ts + (42 + CON.CPS x 4) x tBC + 2 x tDIV
for 8-bit conv.5) for 10-bit conv.5) for 12-bit conv.5) for 8-bit conv. for 10-bit conv. for 12-bit conv. -
Total unadjusted error
TUE6) CC
- - -
- - - -
1 2 6 +5 0 +5
Overload current7)
IAOV1 CC
8)
-2 -2 0 -4 -4 0
kA = 1.0 x 10-3 kA = 1.0 x 10-4
-
IAOV2 CC
9)
-
+10 0 +10
kA = 1.0 x 10-3 kA = 1.0 x 10-4
Data Sheet
73
V1.2, 2002-05
TC1775
Preliminary AD Converter Characteristics (cont'd) TA = -40 C to +125 C; VSS = 0 V;
Parameter Overload coupling factor10) Input leakage current at analog inputs Input leakage current at VAGND and VAREF Switched cap. at the positive reference voltage input Switched cap. at the negative reference voltage input Total cap. at the analog voltage input Switched cap. at the analog voltage input Symbol min. Limit Values typ. - - - 15 max. 1.0 x 10-3 1.0 x 10-4 200 500 20 - - nA nA pF see IAOV1 and IAOV2 0 V < VIN < VDDA1) 0 V < VIN < VDDA1)
11)
Unit
Test Conditions
kA
CC
- - - -
IOZ1 CC IOZ2 CC CAREFSW
CC
CAGNDS
CC
-
15
20
pF
11)
CAINTOT
CC
- - -
12 - -
15 10 0.7
pF pF k
-
12)
CAINSW
CC
ON resistance of the RAIN CC transmission gates in the analog voltage path
1) 2) 3)
-
VDDAx = VDDA0 for A/D Converter ADC0 and VDDAx = VDDA1 for A/D Converter ADC1. VSSAx = VSSA0 for A/D Converter ADC0 and VSSAx = VSSA1 for A/D Converter ADC1.
The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range. The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range. Definitions for CPS, STC, tBC and tDIV see Figure 25. TUE is tested at VAREF = 5 V, VAGND = 0 V and VDDM = 4.9 V. Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the specified operating range (i.e. VAOV > VDDM + 0.5 V or VAOV < VSSM - 0.5 V) or a short circuit condition occurs on the respective ADC pin. The absolute sum of input currents on all port pins must not exceed 10 mA at any time. The supply voltage (VDD, VDDA0, VDDA1 and VSS, VSSA0, VSSA1) must remain within the specified limits. Under short-circuit conditions the corresponding pin is not ready for use. Applies for one analog input pin. Applies for two adjacent analog input pins.
4)
5) 6) 7)
8) 9)
Data Sheet
74
V1.2, 2002-05
TC1775
Preliminary
10)
The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to the resulting leakage current (Ileak) into an adjacent pin: |Ileak| = kA x |IOV|. Thus under overload conditions an additional error leakage voltage (UAEL) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (RAIN). That means UAEL = RAIN x |Ileak|. See also section 7.1.6 "Error Through Overload Conditions" in the TC1775 Peripheral Units User's Manual for further explanations. This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. Alternatively, the redistributed charge could be specified. The switched capacitance at the analog voltage input must be charged within the sampling time. Alternatively, the redistributed charge could be specified.
11)
12)
R A IN , S o u rce
R A IN , O n
A /D C o nv erte r
V A IN
=
C A IN , B lo ck
C A IN T O T - C A IN S W
C A IN S W
M C S 04879
Figure 24
Equivalent Circuitry of Analog Input
Note: This equivalent circuitry for an analog input is also valid for the reference inputs VAREF and VAGND.
Data Sheet
75
V1.2, 2002-05
TC1775
Preliminary
A/D Converter Module Peripheral Clock Divider (1:1) to (1:8)
fADC
fDIV
Programmable Clock Divider (1:1) to (1:128)
fBC
4:1 3:1
fANA
Programmable Counter
Sample Time tS
CON.PCD Arbiter (1:20)
CON.CTC
CON.CPS
CHCONn.STC
fTIMER
Control Unit (Timer)
Control/Status Logic Interrupt Logic External Trigger Logic External Multiplexer Logic Request Generation Logic
MCA04657
Figure 25
ADC Clock Circuit
Note: The frequency of fADC is the system clock frequency (fSYS) divided by the value of bit field ADCx_CLC.RMC. Oscillator Pins (Class C Pins)
TA = -40 C to +125 C; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V;
Parameter Input low voltage at XTAL1, XTAL3 Input high voltage at XTAL1, XTAL3 Symbol Limit Values min. max. 0.3 x V V - - 0 V < VIN < VDDOSC 0 V < VIN < VDDOSC 0 V< VIN < VDDOSC Unit Test Conditions
VILX SR -0.5
VIHX SR 0.7 x VDDOSC Input current at XTAL1 IIX1 CC - Input current at XTAL3 IIX3 CC - Input leakage current IOZ CC -
XTAL1, XTAL3
1)
VDDOSC VDDOSC
+ 0.5
20 0.5 200
A A
nA
1)
Only applicable in deep sleep mode.
Data Sheet
76
V1.2, 2002-05
TC1775
Preliminary Power Supply Current
TA = -40 C to +125 C;
Parameter Active mode supply current Symbol Limit Values min. typ.1) max. - - - - - - - Idle mode supply current IID Sleep mode supply current Deep sleep mode supply current Stand-by pin power supply current
1) 2)
Unit Test Conditions mA mA mA mA mA mA mA mA mA PORST = VIL2)3) Sum of IDDS4)
IDD
CC
- 266 36 4 219 34) 4 80 50 4 1 1
250 320 - - - 805) - 200 160 1000 200 120
CC CC CC CC
- - - - -
ISL IDS ISB
IDD at VDDP054) IDD at VDDP8134) IDD at VDD and VDDSRAM4) IDD at VDDSB IDD at VDDSC and VDDAx4) PORST = VIH1)2)6)7) PORST = VIH1)2)7)
PORST = VIH8)
A A A
IDD at VDDSB9)
10)
Parameters in this column are tested at 25 C, 40 MHz system clock (if applicable) and nominal VDD voltages. These parameters are tested at VDDmax and 40 MHz system clock with all outputs disconnected and all inputs at VIL or VIH. These power supply currents are defined as the sum of all currents at the VDD power supply lines: VDD + VDDP05 + VDDP813 + VDDSRAM + VDDSB + VDDPLL + VDDOSC + VDDSC + VDDM + VDDA0 + VDDA1 These power consumption characteristics are measured while running a typical application pattern. The power consumption of modules can increase or decrease using other application programs. The PLL is inactive during this measurement. This parameter has been evaluated at design characterization using an untypical test pattern that makes extensive usage of the SBSRAM. All peripherals are enabled and in idle state. Guaranteed by design characterization.
3)
4)
5)
6) 7) 8) 9) 10)
IDS is the sum of all power supply currents except VDDSB.
TC1775 in deep sleep mode. All other VDD pins are at 0V; TJ = 150 C; VDDSB = 2.0 V.
Data Sheet
77
V1.2, 2002-05
TC1775
Preliminary AC Characteristics Output Rise/Fall Times Class A drivers (GPIO/peripheral ports 8 to 13): VDDP813 = 4.5 to 5.25 V; VSS = 0 V Class B drivers (Bus interface ports 0 to 5): VDDP05 = 2.30 to 2.75 V; VSS = 0 V
TA = -40 C to +125 C, unless otherwise noted; fSYS = 40 MHz
Parameter Symbol Limit Values min. typ. Class A Pins Nominal output rise/ fall time1) max. Unit Test Conditions
tRFAnom
CC
-
5
-
ns
TA = 25 C, CL = 50 pF, VDDP813 = 5.0 V
Px_POCON.PEC = 00B Px_POCON.PDC = 0XB
Maximal output rise/ fall time1) Slow output rise/fall time1)
tRFAmax
CC
-
-
12
ns
CL = 50 pF
Px_POCON.PEC = 00B Px_POCON.PDC = 0XB
tRFAslow
CC
-
-
55
ns
CL = 100 pF
Px_POCON.PEC = 01B Px_POCON.PDC = 0XB
Class B Pins Output rise/fall time1) tRFBmax CC - - - - 4 7 ns ns for CLKOUT CL = 50 pF for all Class B pins except CLKOUT CL = 50 pF
1)
Measured from 10% output level to 90% output level and vice versa.
Data Sheet
78
V1.2, 2002-05
TC1775
Preliminary Testing Waveforms
TA = -40 C to +125 C; Frequency: max. 40 MHz; Class A Pins: VDDP813 = 3.0 to 5.25 V; VSS = 0 V;
VIHmin
VOHmin
Test Points
VOHmin VOLmax
MCT04880
VILmax
VOLmax
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0. Timing measurements are made at VOHmin for a logic 1 and VOLmax for a logic 0. Input and Output Low/High max./min. voltages are defined at Page 68.
Figure 26
Testing Waveforms for Class A Pins
Class B and Class C Pins: VDD = 2.30 to 2.75 V; VSS = 0 V; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V;
VIHmin VDD / 2 VILmax
Test Points
VDD / 2
MCT04881
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0. Timing measurements are made at VDD/2 for a logic 1 and for a logic 0. Input Low/High max./min. voltages are defined at Page 69 and Page 76.
Figure 27
Testing Waveforms for Class B and Class C Pins
VLoad + 0.1 V VLoad - 0.1 V
Timing Reference Points
VOH - 0.1 V VOL - 0.1 V
MCT05074
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 15 mA).
Figure 28
Data Sheet
Tri-State Testing Waveforms for Class B Pins
79 V1.2, 2002-05
TC1775
Preliminary Input Clock Timing
VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; TA = -40 C to +125 C;
Parameter Oscillator clock frequency Symbol min. direct drive fOSC SR (= 1/tOSC) with PLL 1 10 - 10 7 7 - - Limit Values max. 16 16 40 30 - - 4 4 MHz MHz MHz MHz ns ns ns ns Unit
Input clock frequency driving direct drive 1/tOSCDD SR at XTAL1 with PLL Input clock high time Input clock low time Input clock rise time Input clock fall time
t1 t2 t3 t4
SR SR SR SR
tOSC
Input Clock at XTAL1 0.5 VDDOSC
t1
t2
t4
t3
VIHX VILX
MCT04882
Figure 29
Input Clock Timing
Data Sheet
80
V1.2, 2002-05
TC1775
Preliminary CLKOUT Timing
VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Clock period Clock high time Clock low time Clock rise time Clock fall time Clock duty cycle t5/(t5 + t6) Symbol min. Limit Values typ. - - - - - 50 max. - - - 4 4 55 ns ns ns ns ns % 25 Unit
tCLKOUT
CC
t5 t6 t7 t8 DC
CC 7.5 CC 7.5 CC - CC - CC 45
tCLKOUT
CLKOUT 0.5 VDDP05
t5
t6
t8
t7
0.9 VDDP 0.1 VDDP
MCT04883
Figure 30
CLKOUT Output Clock Timing
Data Sheet
81
V1.2, 2002-05
TC1775
Preliminary PLL Parameters Note: All PLL characteristics defined on this and the next page are guaranteed by design characterization.
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 C to +125 C;
Parameter Accumulated jitter VCO frequency range PLL base frequency PLL lock-in time Phase Locked Loop Operation When PLL operation is enabled and configured (see Figure 18 and Page 59), the PLL clock fVCO (and with it the system clock fSYS) is constantly adjusted to the selected frequency. The relation between fVCO and fSYS is defined by: fVCO = K x fSYS. The PLL causes a jitter of fSYS and also of CLKOUT, which is directly derived from fSYS and which has its frequency. The following two formulas define the (absolute) approximate maximum value of jitter DN in ns dependent on the K-factor, the system clock frequency fSYS in MHz, and the number P of consecutive fSYS periods. for P < 23.5 Symbol Limit Values min. max. - MHz MHz 200 130 200 see Figure 31 150 40 - Unit
DN fVCO fPLLBASE tL
s
K
DN [ns] =
3.9 x P + 1.2 fSYS [MHz]
[1]
for P >
23.5
K
DN [ns] =
91.7
fSYS [MHz] x K
+ 1.2
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a value of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum accumulated jitter remains at a constant value. Further, a lower system clock frequency fSYS results in a higher maximum jitter. Figure 31 gives an example for the jitter curves with K = 8.
Data Sheet
82
V1.2, 2002-05
TC1775
Preliminary
2.0 ns
MCD05237
DN
K=8
1.6
1.4
20 MHz 25 MHz 33 MHz 40 MHz
1.2
1.0
0
1
2
3
4
5
6
P DN = Max. jitter P = Number of consecutive fSYS periods K = K-divider of PLL
Figure 31
Approximated Maximum Accumulated PLL Jitter (for K = 8)
Note: For safe clock generation and PLL operation the definitions and restrictions as defined at pages 58, 59, and 80 must be regarded.
Data Sheet
83
V1.2, 2002-05
TC1775
Preliminary EBU Demultiplexed Timing
VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Output delay from CLKOUT Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT Data valid after CLKOUT Data setup to CLKIN Data hold from CLKIN
1) 2)
Symbol min.
Limit Values max. 9 4 - - - 0 -2 9 1 2
Unit ns ns ns ns ns ns ns
1) 1)
2) 2)
t10 t11 t12 t13 t15 t31 t32
CC CC SR SR CC SR SR
see Page 90 - see Page 90 -
Valid for EBU_BUSCONx.26 = 0. Valid for EBU_BUSCONx.26 = 1 (early sample feature). Not applicable for TC1775 BA11 step.
Data Sheet
84
V1.2, 2002-05
TC1775
Preliminary
CLKOUT
CLKIN A[25:0] CODE SVM
1)
t10
Address Valid
t11
ADV
t11
t10
CSx
t10
t11
RD
t11
RD/WR
t13 t12
D[31:0] Normal Sampling D[31:0] Early Sampling BC[3:0]
MCT05075
Data Valid
t31 t10 t11
t32
Data Valid
t11
t10
1) Early
sampling for D[31:0] not available in TC1775 BA11 step.
Figure 32
EBU Demultiplexed Read Timing
Note: WAIT timing see Figure 36.
Data Sheet
85
V1.2, 2002-05
TC1775
Preliminary
C LK O U T A [2 5 :0 ] C O D E 1) SVM
t1 0
A dd re ss V a lid
t11
t11
ADV
t10
CSx
t10
RD
t11
R D /W R
t11
t1 0
D [31 :0 ] D a ta V a lid
t15
t10
B C [3:0 ]
1)
t11
t11
t10
C O D E rem ain s at hig h leve l d u rin g a d e m ultip lex ed w rite cyc le
M C T 04885
Figure 33
EBU Demultiplexed Write Timing
Data Sheet
86
V1.2, 2002-05
TC1775
Preliminary EBU Multiplexed Timing
VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Output delay from CLKOUT Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT Address and data valid after CLKOUT
1)
Symbol
1)
Limit Values min. max. 10 4 - - -
Unit ns ns ns ns ns
1)
t20 t21 t22 t23 t25
CC -2 CC -2 SR 9 SR 1 CC 2
The following condition is always valid: t25 < t20
C LK O U T
t23 t20
A D [3 1:0] A dd re ss V alid
t25
t22
D a ta In
t20
CODE SVM
t2 0
A LE
t20
t2 0
CSx
t20
t21
RD
t21
R D /W R
t20 t20
B C [3 :0 ]
M C T 04886
t21
t21
Figure 34
Data Sheet
EBU Multiplexed Read Timing
87 V1.2, 2002-05
TC1775
Preliminary
C LK O U T
t20
A D [3 1:0] A d dre ss V alid
t20 t25
D ata O ut
t25
t20
CODE SVM
1)
t2 0
A LE
t20
t2 0
CSx
t20
RD
t21
R D /W R
t21
t20 t20
B C [3 :0 ]
t21
t21
1)
C O D E re m a in s a t h ig h lev el du rin g a m u ltiplex ed w rite cy cle
M C T 04887
Figure 35
EBU Multiplexed Write Timing
Data Sheet
88
V1.2, 2002-05
TC1775
Preliminary WAIT Timing (FPI Bus to external Memory)
VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter WAIT setup to CLKOUT WAIT hold from CLKOUT WAIT setup to CLKOUT WAIT hold from CLKOUT
1)
Symbol min.
Limit Values max. - - - -
Unit ns ns ns ns
t50 t51 t52 t53
SR 141) SR 141) SR 7 SR 2
Guaranteed by design characterization.
Synchronous Mode CLKOUT
t51 t50
WAIT
t51 t50
Asynchronous Mode CLKOUT
t53 t52
WAIT
t53 t52
MCT04888
Figure 36
WAIT Timing (from FPI Bus to external Memory)
Data Sheet
89
V1.2, 2002-05
TC1775
Preliminary EBU Burst Mode Timing
VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Output delay from CLKIN Data setup to CLKIN Data hold from CLKIN
1)
Symbol min.
Limit Values max. 14 - -
Unit ns ns ns
t30 t31 t32
CC 0 SR 21) SR 31)
Guaranteed by design characterization.
C LK IN
t30
A [2 5:2 ]
A ddress V alid
t30
ADV
t30
t30
CS0 CODE
t3 0
t30
RD
t3 0
t30
BAA
t30
t31 t32
D [1 5 :0 ] N ote : W A IT m u st b e 1 d urin g a B urs t M od e R ea d C yc le .
V alid
t31 t32
V alid
M C T 04889
Figure 37
Burst Mode Timing (Instruction Read)
Note: Burst mode and external Flash related application hints are described in a separate application note.
Data Sheet 90 V1.2, 2002-05
TC1775
Preliminary EBU Arbitration Signal Timing
VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Output delay from CLKOUT Data setup to CLKOUT Data hold from CLKOUT Symbol min. Limit Values max. 3 - - ns ns ns Unit
t40 t41 t42
CC - SR SR 8 2
CLKOUT
t40
HLDA Output
t40
t40
BREQ Output
t40
CLKOUT
t41
HOLD Input HLDA Input
t42
t41
t42
MCT04890
Figure 38
EBU Arbitration Signal Timing
Data Sheet
91
V1.2, 2002-05
TC1775
Preliminary EBU External Access Timing
VSS = 0 V, VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter CSFPI, BC[3:0], A[23:2] setup before RD or RD/WR Data valid after RD WAIT active after RD RD/WAIT float after RD Data setup to RD/WR Data hold from RD/WR or RD/WR or RD/WR Symbol min. Limit Values max. - - 11 20 - - ns ns ns ns ns ns Unit
t43 t44 t45 t46 t47 t48
SR 3 CC 2 x tCLKOUT CC - CC - SR 3 SR 3
Data Sheet
92
V1.2, 2002-05
TC1775
Preliminary
R ead Tim ing A [2 3:2] B C [3:0 ] CSFPI V alid A d dre ss & B yte C on trol
t43
RD R D /W R A D [31 :0]
t44
t46
D ata V alid
t45
W A IT
t46
W rite Tim ing A [2 3:2] B C [3:0 ] CSFPI RD V alid A d dre ss & B yte C on trol
t4 3
R D /W R
t47
A D [31 :0]
t48
D a ta V a lid
t45
W A IT
t46
M C T 04891
Figure 39
EBU External Access Timing (external Master to FPI Bus)
Data Sheet
93
V1.2, 2002-05
TC1775
Preliminary Port 5 (Trace Port) Timing This timing is applicable for Port 5 when CPU or PCP trace mode is enabled (SCU_CON.ETEN = 1).
VSS = 0 V; VDDP05 = 2.30 to 2.75 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter Port 5 lines high/low from CLKOUT Symbol min. Limit Values max. 5 ns Unit
t55
CC -4
C LK O U T
t55
P 5 [15 :0] O ld S ta te N e w S tate
M C T 04892
Figure 40
Port 5 Timing
Data Sheet
94
V1.2, 2002-05
TC1775
Preliminary SSC Master Mode Timing
VSS = 0 V; VDDP813 = 4.5 to 5.25 V; TA = -40 C to +125 C; CL = 50 pF;
Parameter SCLK/MTSR low/high from CLKOUT MRST setup to SLCK rising/falling edge MRST hold from SLCK rising/falling edge
1)
Symbol min.
1)
Limit Values max. 7 - - - 142) 142)
Unit ns ns ns
t60 t61 t62
CC SR SR
This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic (P13_POCON.PECx = 00B and P13_POCON.PDCx = 00B). Guaranteed by design characterization.
2)
tCLKOUT
CLKOUT
t60
SCLK MTSR State n-1
t60
t60
State n
State n+1
t61 t62
MRST
Data Valid
MCT04893
Note: The timing diagram assumes the highest possible baud rate operation. (fSSC = fCLKOUT, SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000H)
Figure 41
SSC Master Mode Timing
Data Sheet
95
V1.2, 2002-05
TC1775
Preliminary Package Outlines P-BGA-329 (Plastic Ball Grid Array Package)
22 x 1.27 = 27.94 4 x 1.27 = 5.08 A23 A1
22 x 1.27 = 27.94
4 x 1.27 = 5.08
AC1
1.17 0.05
30
0.35 C
0.6 0.1
(0.56)
o0.76 +0.14 -0.16
329x o0.3 M A B C o0.15 M C
2.52 MAX.
1.27
0.2
C
A
31 0.2
Index Marking
1.95 x 45
4x
26 1 31 0.2
26 1
B
GPA09280
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 96 Dimensions in mm V1.2, 2002-05
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Published by Infineon Technologies AG

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